XC95288-15HQ208C Xilinx Inc, XC95288-15HQ208C Datasheet

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XC95288-15HQ208C

Manufacturer Part Number
XC95288-15HQ208C
Description
IC CPLD SPEED GRADE 208-HQFP/COM
Manufacturer
Xilinx Inc
Series
XC9500r
Datasheets

Specifications of XC95288-15HQ208C

Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
15.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
288
Number Of Gates
6400
Number Of I /o
168
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Voltage
5V
Memory Type
FLASH
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Other names
Q1090654

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DS063 (v5.5) June 25, 2007
Features
Table 1: XC9500 Device Family
DS063 (v5.5) June 25, 2007
Product Specification
1.
2.
Macrocells
Usable Gates
Registers
T
T
T
f
f
CNT
SYSTEM
PD
SU
CO
© 2006, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
High-performance
-
-
Large density range
-
5V in-system programmable
-
-
Enhanced pin-locking architecture
Flexible 36V18 Function Block
-
-
-
-
-
-
-
-
-
f
f
CNT
SYSTEM
(ns)
(ns)
(ns)
(MHz)
5 ns pin-to-pin logic delays on all pins
f
36 to 288 macrocells with 800 to 6,400 usable
gates
Endurance of 10,000 program/erase cycles
Program/erase over full commercial voltage and
temperature range
90 product terms drive any or all of 18 macrocells
within Function Block
Global and product term clocks, output enables,
set and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design
protection
High-drive 24 mA outputs
3.3V or 5V I/O capability
CNT
= Operating frequency for 16-bit counters.
(MHz)
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
(1)
= Internal operating frequency for general purpose system designs spanning multiple FBs.
to 125 MHz
(2)
XC9536
R
800
100
100
3.5
4.0
36
36
5
XC9572
1,600
83.3
125
7.5
4.5
4.5
72
72
0
0
www.xilinx.com
0
XC95108
2,400
83.3
XC9500 In-System Programmable
CPLD Family
Product Specification
Family Overview
The XC9500 CPLD family provides advanced in-system
programming and test capabilities for high performance,
general purpose logic integration. All devices are in-system
programmable for a minimum of 10,000 program/erase
cycles. Extensive IEEE 1149.1 (JTAG) boundary-scan sup-
port is also included on all family members.
As shown in
ranges from 800 to over 6,400 usable gates with 36 to 288
registers, respectively. Multiple package options and asso-
ciated I/O capacity are shown in
ily is fully pin-compatible allowing easy design migration
across multiple density options in a given package footprint.
The XC9500 architectural features address the require-
ments of in-system programmability. Enhanced pin-locking
capability avoids costly board rework. An expanded JTAG
instruction set allows version control of programming pat-
terns and in-system debugging. In-system programming
throughout the full device operating range and a minimum
of 10,000 program/erase cycles provide worry-free recon-
figurations and system field upgrades.
Advanced system features include output slew rate control
and user-programmable ground pins to help reduce system
noise. I/Os may be configured for 3.3V or 5V operation. All
outputs provide 24 mA drive.
108
108
125
7.5
4.5
4.5
-
-
Advanced CMOS 5V FastFLASH™ technology
Supports parallel programming of multiple XC9500
devices
Table
XC95144
3,200
83.3
144
144
125
7.5
4.5
4.5
1, logic density of the XC9500 devices
XC95216
4,800
111.1
66.7
Table
216
216
6.0
6.0
10
2. The XC9500 fam-
XC95288
6,400
92.2
56.6
288
288
8.0
8.0
15
1

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XC95288-15HQ208C Summary of contents

Page 1

... XC9500 devices Table 2. The XC9500 fam- XC95216 XC95288 216 288 4,800 6,400 216 288 7 4.5 6.0 8.0 4.5 6.0 8.0 111.1 92.2 66.7 56 ...

Page 2

... See XCN07010 for details. provides programmable logic capability with 36 inputs and 18 outputs. The Fast CONNECT switch matrix connects all FB outputs and input signals to the FB inputs. For each FB outputs (depending on package pin-count) and www.xilinx.com XC95216 XC95288 - - - - - - - - - - - ...

Page 3

R associated output enable signals drive directly to the IOBs. See Figure 1. 3 JTAG Port I/O I/O I/O I/O I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS Note: Function block outputs (indicated by the bold ...

Page 4

XC9500 In-System Programmable CPLD Family From 36 Fast CONNECT II Switch Matrix 4 Macrocell 1 Product Programmable Term AND-Array Allocators Macrocell 18 1 Global Set/Reset Figure 2: XC9500 Function Block www.xilinx.com 18 To Fast CONNECT II Switch Matrix 18 OUT ...

Page 5

R Macrocell Each XC9500 macrocell may be individually configured for a combinatorial or registered function. The macrocell and associated FB logic is shown in Figure Five direct product terms from the AND-array are available for use as primary data inputs ...

Page 6

XC9500 In-System Programmable CPLD Family All global control signals are available to each individual macrocell, including clock, set/reset, and output enable sig- nals. As shown in Figure 4, the macrocell register clock originates from either of three global clocks or ...

Page 7

R Product Term Allocator The product term allocator controls how the five direct prod- uct terms are assigned to each macrocell. For example, all five direct terms can drive the OR function as shown in Figure 5. Product Term Allocator ...

Page 8

XC9500 In-System Programmable CPLD Family The product term allocator can re-assign product terms from any macrocell within the FB by combining partial sums of products over several macrocells, as shown in In this example, the incremental delay is only 2 ...

Page 9

R The internal logic of the product term allocator is shown in Figure 8. From Upper Macrocell From Lower Macrocell DS063 (v5.5) June 25, 2007 Product Specification XC9500 In-System Programmable CPLD Family To Upper Macrocell Product Term Allocator To Lower ...

Page 10

XC9500 In-System Programmable CPLD Family Fast CONNECT Switch Matrix The Fast CONNECT switch matrix connects signals to the FB inputs, as shown in Figure 9. All IOB outputs (corre- sponding to user pin inputs) and all FB outputs drive the ...

Page 11

... To other Macrocells OUT PTOE Global OE 1 Global OE 2 Global OE 3 Global OE 4 www.xilinx.com ) to ensure that the input thresh- CCINT CCIO I/O Block V CCIO Pull-up Resistor* 1 User- Programmable Ground 0 Slew Rate Control Available in XC95216 and XC95288 DS063_10_092203 voltage. I/O 11 ...

Page 12

XC9500 In-System Programmable CPLD Family Each output has independent slew rate control. Output edge rates may be slowed down to reduce system noise (with an additional time delay of T SLEW ming. See Figure 11. Each IOB provides user programmable ...

Page 13

R In-System Programming XC9500 devices are programmed in-system via a standard 4-pin JTAG protocol, as shown in Figure gramming offers quick and efficient design iterations and eliminates package handling. The Xilinx development sys- tem provides the programming data sequence using ...

Page 14

XC9500 In-System Programmable CPLD Family Figure 13: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable Low Power Mode All XC9500 devices offer a low-power mode for individual macrocells or across all macrocells. This feature ...

Page 15

R Combinatorial Logic Propagation Delay = T (a) T PSU Combinatorial Logic P-Term Clock Path Setup Time = T PSU (c) All resources within FB using local Feedback Combinatorial Logic Internal Cycle Time = T ( GCK ...

Page 16

XC9500 In-System Programmable CPLD Family Power-Up Characteristics The XC9500 devices are well behaved under all operating conditions. During power-up each XC9500 device employs internal circuitry which keeps the device in the quiescent state until the V supply voltage is at ...

Page 17

... Version 3.0 12/14/98 Revised datasheet to reflect new AC characteristics and Internal Timing Parmeters. 4.0 02/10/99 Corrected Figure 3. 5.0 09/15/99 Added -10 speed grade to XC95288. 5.1 09/22/03 Minor edits. 5.2 02/16/04 Corrected statement on GTS inputs on page 10. Added links to additional information. 5.3 04/15/05 Update to PDF attributes only. No changes to documentation. ...

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