XC95288XV-7CS280C Xilinx Inc, XC95288XV-7CS280C Datasheet - Page 14

• Manufacturer Part Number: XC95288XV-7CS280C
• Description: IC CPLD 2.5V ISP 280-CSP
• Manufacturer: Xilinx Inc
• Series: XC9500XVr

Specifications of XC95288XV-7CS280C

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 2.37 V ~ 2.62 V
• Number Of Logic Elements/blocks: 16
• Number Of Macrocells: 288
• Number Of Gates: 6400
• Number Of I /o: 192
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 280-CSBGA
• Voltage: 2.5V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -

XC9500XV Family High-Performance CPLD
Mixed Voltage
The I/Os on each XC9500XV device are fully 3.3V tolerant
even though the core power supply is 2.5V. This allows 3.3V
CMOS signals to connect directly to the XC9500XV inputs
without damage. In addition, the 2.5V V
can be applied before or after 2.5V signals are applied to
the I/Os. In mixed 3.3V/2.5V/1.8V systems, the user pins,
the core power supply (V
ply (V
makes the XC9500XV devices immune to power supply
sequencing problems (see
Xilinx proprietary ESD circuitry and high impedance initial
state permit hot plugging cards using XC9500XV CPLDs.
Pin-Locking Capability
The capability to lock the user defined pin assignments dur-
ing design iteration depends on the ability of the architec-
ture to adapt to unexpected changes. The XC9500XV
devices incorporate architectural features that enhance the
ability to accept design changes while maintaining the same
pinout.
The XC9500XV architecture provides for superior pin-lock-
ing characteristics with a combination of large number of
routing switches in the Fast CONNECT II switch matrix, a
54-wide input Function Block, and flexible, bidirectional
product term allocation within each macrocell. These fea-
tures address design changes that require adding or chang-
ing internal routing, including additional signals into existing
equations, or increasing equation complexity, respectively.
For extensive design changes requiring higher logic capac-
ity than is available in the initially chosen device, the new
design may be able to fit into a larger pin-compatible device
using the same pin assignments. The same board may be
14
Figure 15: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
CCIO
) may have power applied in any order. This
CCINT
Figure
), and the output power sup-
11b).
(a)
CCINT
power supply
www.xilinx.com
used with a higher density device without the expense of
board rework.
In-System Programming
One or more XC9500XV devices can be daisy chained
together and programmed in-system via a standard 4-pin
JTAG protocol, as shown in
ming offers quick and efficient design iterations and elimi-
nates package handling. The Xilinx development system
provides the programming data sequence using a Xilinx
download cable, a third-party JTAG development system,
JTAG-compatible board tester, or a simple microprocessor
interface that emulates the JTAG instruction sequence.
All I/Os are set to a high-impedance state and pulled High
by the bus-hold circuitry during in-system programming. If a
particular signal must remain Low during this time, then a
pull-down resistor may be added to the pin.
Reliability and Endurance
All XC9500XV CPLDs provide a minimum endurance level
of 1,000 in-system program/erase cycles and a minimum
data retention of 20 years. Each device meets all functional,
performance, and data retention specifications within this
endurance limit.
IEEE 1149.1 Boundary-Scan (JTAG)
XC9500XV devices fully support IEEE 1149.1 bound-
ary-scan (JTAG). EXTEST, SAMPLE/PRELOAD, BYPASS,
USERCODE, INTEST, IDCODE, HIGHZ, and CLAMP
instructions are supported in each device. Additional
instructions are included for in-system programming opera-
tions.
(b)
Figure
DS049 (v3.0) June 25, 2007
15. In-system program-
X5902
Product Specification
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