XC95288XV-7CS280C Xilinx Inc, XC95288XV-7CS280C Datasheet
XC95288XV-7CS280C
Specifications of XC95288XV-7CS280C
Available stocks
Related parts for XC95288XV-7CS280C
XC95288XV-7CS280C Summary of contents
Page 1
... Lower power operation - Multi-voltage operation - FastFLASH technology • Advanced system features - In-system programmable - Output banking (XC95144XV, XC95288XV) - Superior pin-locking and routability with Fast CONNECT™ II switch matrix - Extra wide 54-input Function Blocks - product-terms per macrocell with individual product-term allocation - Local clock inversion with three global and one ...
Page 2
... Figure 1. In-System Programming Controller 54 Function Block 1 18 Macrocells Function Block 2 18 Macrocells Function Block 3 18 Macrocells Function Block N 18 Macrocells DS049_01_041400 XC95144XV XC95288XV 144 288 3,200 6,400 144 288 5 3.5 DS049 (v3.0) June 25, 2007 Product Specification ...
Page 3
... AND-array to form 90 product terms. Any number of these product terms the 90 available, can be allocated to each macrocell by the product term allocator. www.xilinx.com XC9500XV Family High-Performance CPLD XC95144XV XC95288XV 3.5 3.8 222 208 2 4 (1) XC95144XV XC95288XV - 81 - 117 - 117 117 - 168 - 192 - 192 - 3 ...
Page 4
XC9500XV Family High-Performance CPLD From 54 Fast CONNECT II Switch Matrix Macrocell Each XC9500XV macrocell may be individually configured for a combinatorial or registered function. The macrocell and associated FB logic is shown in Five direct product terms from the ...
Page 5
R 54 Allocator Figure 3: XC9500XV Macrocell Within Function Block Note: See DS049 (v3.0) June 25, 2007 Product Specification Global Global Set/Reset Clocks 3 Additional Product Terms (from other macrocells) Product Term Set 1 0 Product Term Product Term Clock ...
Page 6
XC9500XV Family High-Performance CPLD All global control signals are available to each individual macrocell, including clock, set/reset, and output enable sig- nals. As shown in Figure 4, the macrocell register clock originates from either of three global clocks or a ...
Page 7
R Product Term Allocator The product term allocator controls how the five direct prod- uct terms are assigned to each macrocell. For example, all five direct terms can drive the OR function as shown in Figure 5. Product Term Allocator ...
Page 8
XC9500XV Family High-Performance CPLD The product term allocator can re-assign product terms from any macrocell within the FB by combining partial sums of products over several macrocells, as shown in In this example, the incremental delay is only 2 product ...
Page 9
R The internal logic of the product term allocator is shown in Figure 8. From Upper Macrocell From Lower Macrocell DS049 (v3.0) June 25, 2007 Product Specification To Upper Macrocell Product Term Allocator To Lower Macrocell Figure 8: Product Term ...
Page 10
XC9500XV Family High-Performance CPLD Fast CONNECT II Switch Matrix The Fast CONNECT II Switch Matrix connects signals to the FB inputs, as shown in Figure 9. All IOB outputs (corre- sponding to user pin inputs) and all FB outputs drive ...
Page 11
... See details. To other Macrocells OUT PTOE Global OE 1 Global OE 2 Global OE 3 Global OE 4 www.xilinx.com XC9500XV Family High-Performance CPLD I/O Block Bus-Hold 1 User- Programmable Ground 0 Slew Rate Control Available in XC95144XV and XC95288XV DS049_10_041400 Figure 10 for I/O 11 ...
Page 12
XC9500XV Family High-Performance CPLD The input buffer is compatible with 3.3V CMOS and 2.5V CMOS signals. The input buffer uses the internal 2.5V volt- age supply ( ensure that the input thresholds are CCINT constant and do not ...
Page 13
... Time 0 Output Banking XC95288XV and XC95144XV devices are designed with a split-rail I/O structure. This permits the utilization of multiple output drive levels for systems able to operate best in that environment. The output partitioning is by function blocks (FB). With this arrangement, designers can have some sets of outputs driving to 2 ...
Page 14
XC9500XV Family High-Performance CPLD Mixed Voltage The I/Os on each XC9500XV device are fully 3.3V tolerant even though the core power supply is 2.5V. This allows 3.3V CMOS signals to connect directly to the XC9500XV inputs without damage. In addition, ...
Page 15
R Design Security XC9500XV devices incorporate advanced data security fea- tures which fully protect the programming data against unauthorized reading or inadvertent device erasure/repro- gramming. Table 3 shows the four different security settings available. The read security bits can be ...
Page 16
XC9500XV Family High-Performance CPLD Combinatorial Logic Propagation Delay = T (a) T PSU Combinatorial Logic P-Term Clock Path Setup Time = T PSU (c) Table 4: Timing Model Parameters Description Propagation Delay Global Clock Setup Time Global Clock-to-output Product Term ...
Page 17
GCK T GSR T GTS Power-Up Characteristics The XC9500XV devices are well behaved under all operat- ing conditions. During power-up each XC9500XV device employs internal circuitry which keeps the device in the qui- escent state until ...
Page 18
XC9500XV Family High-Performance CPLD Power-Up Guidelines Figure 19 shows a block diagram of the internal configura- tion controller, which transfers the EPROM bits to the latches. Some important things to note are: • The V is sensed to determine when ...
Page 19
R Revision History The following table shows the revision history for this document. Date Version 01/19/99 1.0 Initial Xilinx release. Advance Information Specification. 06/12/00 1.1 Updated 3.3V information, added Output Banking, added DS049 number. Added WebPACK information and minor edits. ...