XC95288-15BG352I Xilinx Inc, XC95288-15BG352I Datasheet - Page 12

• Manufacturer Part Number: XC95288-15BG352I
• Description: IC CPLD 288 MCELL I-TEMP 352-BGA
• Manufacturer: Xilinx Inc
• Series: XC9500r

Specifications of XC95288-15BG352I

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 4.5 V ~ 5.5 V
• Number Of Logic Elements/blocks: 16
• Number Of Macrocells: 288
• Number Of Gates: 6400
• Number Of I /o: 192
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 352-MBGA
• Voltage: 5V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -

XC9500 In-System Programmable CPLD Family
Each output has independent slew rate control. Output
edge rates may be slowed down to reduce system noise
(with an additional time delay of T
ming. See
Each IOB provides user programmable ground pin capabil-
ity. This allows device I/O pins to be configured as additional
ground pins. By tying strategically located programmable
ground pins to the external ground connection, system
noise generated from large numbers of simultaneous
switching outputs may be reduced.
A control pull-up resistor (typically 10K ohms) is attached to
each device I/O pin to prevent them from floating when the
device is not in normal user operation. This resistor is active
during device programming mode and system power-up. It
is also activated for an erased device. The resistor is deac-
tivated during normal operation.
The output driver is capable of supplying 24 mA output
drive. All output drivers in the device may be configured for
either 5V TTL levels or 3.3V levels by connecting the device
output voltage supply (V
12
5V CMOS or
5V TTL or
3.3V
1.5V
3.6V
3.3V
5V
0V
0V
0V
Voltage
Output
Figure
0
11.
IN
Standard
Figure 12: XC9500 Devices in (a) 5V Systems and (b) Mixed 5V/3.3V Systems
V
CCINT
T
5V
SLEW
CCIO
XC9500
CPLD
Figure 11: Output slew-Rate for (a) Rising and (b) Falling Outputs
GND
(a)
) to a 5V or 3.3V voltage sup-
V
CCIO
(a)
OUT
SLEW
Slew-Rate Limited
) through program-
5V TTL
–4V
0V
www.xilinx.com
Time
ply.
in 5V only and mixed 3.3V/5V systems.
Pin-Locking Capability
The capability to lock the user defined pin assignments dur-
ing design changes depends on the ability of the architec-
ture to adapt to unexpected changes. The XC9500 devices
have architectural features that enhance the ability to
accept design changes while maintaining the same pinout.
The XC9500 architecture provides maximum routing within
the Fast CONNECT switch matrix, and incorporates a flexi-
ble Function Block that allows block-wide allocation of avail-
able product terms. This provides a high level of confidence
of maintaining both input and output pin assignments for
unexpected design changes.
For extensive design changes requiring higher logic capac-
ity than is available in the initially chosen device, the new
design may be able to fit into a larger pin-compatible device
using the same pin assignments. The same board may be
used with a higher density device without the expense of
board rework
1.5V
5V CMOS or
5V TTL or
3.3V
Voltage
Output
Figure 12
0
3.6V
3.3V
5V
0V
0V
0V
T
SLEW
Standard
shows how the XC9500 device can be used
Slew-Rate Limited
IN
V
5V
CCINT
XC9500
CPLD
GND
(b)
(b)
V
3.3V
CCIO
DS063 (v5.5) June 25, 2007
OUT
Product Specification
DS063_11_110501
3.3V
DS063_12_110501
Time
3.3V
0V
R