XC95288-15BG352I Xilinx Inc, XC95288-15BG352I Datasheet

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XC95288-15BG352I

Manufacturer Part Number
XC95288-15BG352I
Description
IC CPLD 288 MCELL I-TEMP 352-BGA
Manufacturer
Xilinx Inc
Series
XC9500r
Datasheets

Specifications of XC95288-15BG352I

Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
15.0ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
288
Number Of Gates
6400
Number Of I /o
192
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
352-MBGA
Voltage
5V
Memory Type
FLASH
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-

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XC95288-15BG352I
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0
DS069 (v4.3) April 3, 2006
Features
DS069 (v4.3) April 3, 2006
Product Specification
© 1996-2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
15 ns pin-to-pin logic delays on all pins
f
288 macrocells with 6,400 usable gates
Up to 166 user I/O pins
5V in-system programmable
-
-
Enhanced pin-locking architecture
Flexible 36V18 Function Block
-
-
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design
protection
High-drive 24 mA outputs
3.3V or 5V I/O capability
Advanced CMOS 5V FastFLASH™ technology
Supports parallel programming of more than one
XC9500 concurrently
Available 352-pin BGA and 208-pin HQFP packages
CNT
Endurance of 10,000 program/erase cycles
Program/erase over full commercial voltage and
temperature range
90 product terms drive any or all of 18 macrocells
within Function Block
Global and product term clocks, output enables,
set and reset signals
to 95 MHz
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
R
0
0
www.xilinx.com
5
XC95288 In-System
Programmable CPLD
Product Specification
Description
The XC95288 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 15 ns. See
ture overview.
Power Management
Power dissipation can be reduced in the XC95288 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
Where:
Figure 1
device.
CC
(mA) = MC
(500)
Figure 1: Typical I
MC
MC
MC = Total number of macrocells used
f = Clock frequency (MHz)
900
600
300
0
HP
LP
shows a typical calculation for the XC95288
= Macrocells in low-power mode
= Macrocells in high-performance mode
HP
(1.7) + MC
Clock Frequency (MHz)
CC
vs. Frequency for XC95288
LP
50
(0.9) + MC (0.006 mA/MHz) f
Figure 2
for the architec-
DS069_01_110101
100
(700)
(500)
1

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XC95288-15BG352I Summary of contents

Page 1

... Function Blocks, providing 6,400 usable gates with propagation delays of 15 ns. See ture overview. Power Management Power dissipation can be reduced in the XC95288 by con- figuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for ...

Page 2

... I/O I/O I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 2 I/O/GTS Function block outputs (indicated by the bold line) drive the I/O blocks directly. 2 JTAG In-System Programming Controller Controller I/O Blocks Figure 2: XC95288 Architecture www.xilinx.com 36 Function 18 Block 1 Macrocells Function 18 Block 2 Macrocells Function 18 Block 3 Macrocells ...

Page 3

... –3 Max GND Max GND GND 1.0 MHz V = GND, No load 1.0 MHz www.xilinx.com XC95288 In-System Programmable CPLD Value –0.5 to 7.0 –0 0.5 CC –0 0.5 CC –65 to +150 +150 Min Max o C 4.75 5. 4.5 5 4.75 5. 4.5 5.5 3.0 3.6 0 0.80 2 0.5 CCINT ...

Page 4

... XC95288 In-System Programmable CPLD AC Characteristics Symbol Parameter T I/O to output valid PD T I/O setup time before GCK SU T I/O hold time after GCK H T GCK to output valid CO (1) f 16-bit counter frequency CNT (2) f Multiple FB internal operating frequency SYSTEM T I/O setup time before p-term clock input ...

Page 5

... Incremental product term allocator delay PTA T Slew-rate limited delay SLEW Notes multiplied by the span of the function as defined in the XC9500 family data sheet. PTA DS069 (v4.3) April 3, 2006 Product Specification Parameter www.xilinx.com XC95288 In-System Programmable CPLD XC95288-15 XC95288-20 Min Max Min Max - 4.5 - 6 ...

Page 6

... XC95288 In-System Programmable CPLD XC95288 I/O Pins Function Block Macrocell HQ208 1 1 – – – – – – – – – – – – – – – – Notes: 1. Global control pin. 6 BScan Function BG352 Order Block – 861 3 N26 858 ...

Page 7

... B22 564 8 C21 561 8 D20 558 8 – 555 8 B24 552 8 [1] C23 549 8 – 546 8 D22 543 8 – 540 8 www.xilinx.com XC95288 In-System Programmable CPLD Macrocell HQ208 BG352 1 – – AC19 3 63 AD19 4 – – AE20 6 66 AC18 7 – – AD18 9 – ...

Page 8

... XC95288 In-System Programmable CPLD XC95288 I/O Pins (Continued) Function Block Macrocell HQ208 9 1 – – – – – – – – 170 10 3 171 10 4 – 173 10 6 174 10 7 – 175 10 9 – 178 10 11 179 10 12 180 10 13 – ...

Page 9

... G2 132 16 G3 129 16 F2 126 16 – 123 16 E2 120 16 D2 117 16 – 114 16 F4 111 16 – 108 16 www.xilinx.com XC95288 In-System Programmable CPLD Macrocell HQ208 BG352 1 – – 2 117 V3 3 118 W2 4 – – 5 119 U4 6 120 U3 7 – – 8 121 V2 9 – ...

Page 10

... XC95288 In-System Programmable CPLD XC95288 Global, JTAG, and Power Pins Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI TDO TMS V 5V CCINT V 3.3V/5V CCIO GND No Connects 10 HQ208 206 98 94 176 96 11, 59, 124, 153, 204 1, 26, 53, 65, 79, 92, 105, 132, 157, ...

Page 11

... Operating Range Speed Device Ordering and (pin-to-pin Part Marking Number delay) XC95288-10HQ208C 10 ns XC95288-10BG352C 10 ns XC95288-15HQ208C 15 ns XC95288-15BG352C 15 ns XC95288-15HQ208I 15 ns XC95288-15BG352I 15 ns XC95288-20HQ208C 20 ns XC95288-20BG352C 20 ns XC95288-20HQ208I 20 ns XC95288-20BG352I 20 ns Notes Commercial 0° to +70° Industrial Warranty Disclaimer THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www ...

Page 12

... XC95288 In-System Programmable CPLD Date Version 08/21/03 4.1 Updated Package Device Marking Pin 1 orientation. 04/15/05 4.2 Added asynchronous preset/reset pulse width specification (T 04/03/06 4.3 Added Warranty Disclaimer. 12 Revision www.xilinx.com R ). APRPW DS069 (v4.3) April 3, 2006 Product Specification ...

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