XC95288-15BG352I Xilinx Inc, XC95288-15BG352I Datasheet - Page 13

• Manufacturer Part Number: XC95288-15BG352I
• Description: IC CPLD 288 MCELL I-TEMP 352-BGA
• Manufacturer: Xilinx Inc
• Series: XC9500r

Specifications of XC95288-15BG352I

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 4.5 V ~ 5.5 V
• Number Of Logic Elements/blocks: 16
• Number Of Macrocells: 288
• Number Of Gates: 6400
• Number Of I /o: 192
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 352-MBGA
• Voltage: 5V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -

In-System Programming
XC9500 devices are programmed in-system via a standard
4-pin JTAG protocol, as shown in
gramming offers quick and efficient design iterations and
eliminates package handling. The Xilinx development sys-
tem provides the programming data sequence using a Xilinx
download cable, a third-party JTAG development system,
JTAG-compatible board tester, or a simple microprocessor
interface that emulates the JTAG instruction sequence.
All I/Os are 3-stated and pulled high by the IOB resistors
during in-system programming. If a particular signal must
remain Low during this time, then a pulldown resistor may
be added to the pin.
External Programming
XC9500 devices can also be programmed by the Xilinx
HW130 device programmer as well as third-party program-
mers. This provides the added flexibility of using pre-pro-
grammed devices during manufacturing, with an in-system
programmable option for future enhancements.
Endurance
All XC9500 CPLDs provide a minimum endurance level of
10,000 in-system program/erase cycles. Each device meets
all functional, performance, and data retention specifica-
tions within this endurance limit.
IEEE 1149.1 Boundary-Scan (JTAG)
XC9500 devices fully support IEEE 1149.1 boundary-scan
(JTAG). EXTEST, SAMPLE/PRELOAD, BYPASS, USER-
CODE, INTEST, IDCODE, and HIGHZ instructions are sup-
ported in each device. For ISP operations, five additional
instructions are added; the ISPEN, FERASE, FPGM, FVFY,
and ISPEX instructions are fully compliant extensions of the
1149.1 instruction set.
DS063 (v5.5) June 25, 2007
Product Specification
R
Figure
13. In-system pro-
www.xilinx.com
The TMS and TCK pins have dedicated pull-up resistors as
specified by the IEEE 1149.1 standard.
Boundary Scan Description Language (BSDL) files for the
XC9500 are included in the development system and are
available on the Xilinx FTP site.
Design Security
XC9500 devices incorporate advanced data security fea-
tures which fully protect the programming data against
unauthorized reading or inadvertent device erasure/repro-
gramming.
available.
The read security bits can be set by the user to prevent the
internal programming pattern from being read or copied.
When set, they also inhibit further program operations but
allow device erase. Erasing the entire device is the only way
to reset the read security bit.
The write security bits provide added protection against
accidental device erasure or reprogramming when the
JTAG pins are subject to noise, such as during system
power-up. Once set, the write-protection may be deacti-
vated when the device needs to be reprogrammed with a
valid pattern.
Table 3: Data Security Options
Default
XC9500 In-System Programmable CPLD Family
Set
Table 3
shows the four different security settings
Program/Erase
Program/Erase
Read Allowed
Read Allowed
Inhibited
Allowed
Default
Read Security
Program Inhibited
Program/Erase
Read Inhibited
Read Inhibited
Erase Allowed
Inhibited
Set
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