EPM1270F256I5 Altera, EPM1270F256I5 Datasheet - Page 84

IC MAX II CPLD 1270 LE 256-FBGA

EPM1270F256I5

Manufacturer Part Number
EPM1270F256I5
Description
IC MAX II CPLD 1270 LE 256-FBGA
Manufacturer
Altera
Series
MAX® IIr
Datasheets

Specifications of EPM1270F256I5

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.2ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
1270
Number Of Macrocells
980
Number Of I /o
212
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
1270
Family Name
MAX II
# Macrocells
980
Frequency (max)
1.8797GHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
127
# I/os (max)
212
Operating Supply Voltage (typ)
2.5/3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
For Use With
544-2380 - KIT DEV MAXII W/EPM 1270N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1381
EPM1270F256I5

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5–26
Table 5–34. MAX II JTAG Timing Parameters (Part 2 of 2)
Referenced Documents
MAX II Device Handbook
t
t
t
t
t
t
t
t
t
t
Notes to
(1) Minimum clock period specified for 10 pF load on the TDO pin. Larger loads on TDO will degrade the maximum TCK
(2) This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For 1.8-V
JP SU
JP H
JP CO
JP ZX
JP XZ
JS SU
JS H
JS CO
JS ZX
JS XZ
frequency.
LVTTL/LVCMOS and 1.5-V LVCMOS, the t
Symbol
Table
5–34:
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
This chapter references the following documents:
I/O Structure section in the
Handbook
Hot Socketing and Power-On Reset in MAX II Devices
Handbook
Operating Requirements for Altera Devices Data Sheet
PowerPlay Power Analysis
Understanding and Evaluating Power in MAX II Devices
Handbook
Understanding Timing in MAX II Devices
Using MAX II Devices in Multi-Voltage Systems
Handbook
Parameter
JPS U
(2)
minimum is 6 ns and t
(2)
chapter in volume 3 of the Quartus II Handbook
MAX II Architecture
J PC O
(2)
(2)
, t
JP ZX
, and t
Min
10
10
8
8
JP XZ
chapter in the MAX II Device Handbook
are maximum values at 35 ns.
chapter in the MAX II Device
chapter in the MAX II Device
Chapter 5: DC and Switching Characteristics
Max
15
15
15
25
25
25
chapter in the MAX II Device
chapter in the MAX II Device
© August 2009 Altera Corporation
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Referenced Documents

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