EPM1270F256I5 Altera, EPM1270F256I5 Datasheet - Page 14

• Manufacturer Part Number: EPM1270F256I5
• Description: IC MAX II CPLD 1270 LE 256-FBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM1270F256I5

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of I /o: 212
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 2.5V, 3.3V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 1270
• Family Name: MAX II
• # Macrocells: 980
• Frequency (max): 1.8797GHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 127
• # I/os (max): 212
• Operating Supply Voltage (typ): 2.5/3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• For Use With: 544-2380 - KIT DEV MAXII W/EPM 1270N
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1381; EPM1270F256I5

2–6
Figure 2–5. LAB-Wide Control Signals
Logic Elements
MAX II Device Handbook
Dedicated
LAB Column
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
The smallest unit of logic in the MAX II architecture, the LE, is compact and provides
advanced features with efficient logic utilization. Each LE contains a four-input LUT,
which is a function generator that can implement any function of four variables. In
addition, each LE contains a programmable register and carry chain with carry-select
capability. A single LE also supports dynamic single-bit addition or subtraction mode
selectable by an LAB-wide control signal. Each LE drives all types of interconnects:
local, row, column, LUT chain, register chain, and DirectLink interconnects. See
Figure
2–6.
4
labclk1
labclkena1
labclk2
labclkena2
asyncload
or labpre
syncload
labclr1
© October 2008 Altera Corporation
Chapter 2: MAX II Architecture
labclr2
synclr
Logic Elements
addnsub