EPM1270F256I5 Altera, EPM1270F256I5 Datasheet - Page 30

IC MAX II CPLD 1270 LE 256-FBGA

EPM1270F256I5

Manufacturer Part Number
EPM1270F256I5
Description
IC MAX II CPLD 1270 LE 256-FBGA
Manufacturer
Altera
Series
MAX® IIr
Datasheets

Specifications of EPM1270F256I5

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.2ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
1270
Number Of Macrocells
980
Number Of I /o
212
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
1270
Family Name
MAX II
# Macrocells
980
Frequency (max)
1.8797GHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
127
# I/os (max)
212
Operating Supply Voltage (typ)
2.5/3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
For Use With
544-2380 - KIT DEV MAXII W/EPM 1270N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1381
EPM1270F256I5

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2–22
Figure 2–17. EPM570, EPM1270, and EPM2210 UFM Block LAB Row Interface
MultiVolt Core
Figure 2–18. MultiVolt Core Feature in MAX II Devices
MAX II Device Handbook
3.3-V or 2.5-V on
VCCINT Pins
The MAX II architecture supports the MultiVolt core feature, which allows MAX II
devices to support multiple V
regulator provides the necessary 1.8-V internal voltage supply to the device. The
voltage regulator supports 3.3-V or 2.5-V supplies on its inputs to supply the 1.8-V
internal voltage to the device, as shown in
guaranteed for voltages that are between the maximum recommended 2.5-V
operating voltage and the minimum recommended 3.3-V operating voltage.
The MAX IIG and MAX IIZ devices use external 1.8-V supply. The 1.8-V V
supply powers the device core directly.
1.8-V Core
Regulator
Voltage
Voltage
MAX II Device
CFM Block
UFM Block
RTP_BUSY
PROGRAM
DRDSHFT
OSC_ENA
CC
DRDCLK
ARSHFT
DRDout
ERASE
ARCLK
levels on the V
DRDin
ARDin
BUSY
OSC
VCCINT Pins
1.8-V on
Figure
CCINT
2–18. The voltage regulator is not
1.8-V Core
LAB
LAB
LAB
MAX IIG or MAX IIZ Device
Voltage
supply. An internal linear voltage
© October 2008 Altera Corporation
Chapter 2: MAX II Architecture
CC
MultiVolt Core
external

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