EPM1270F256I5 Altera, EPM1270F256I5 Datasheet - Page 32

IC MAX II CPLD 1270 LE 256-FBGA

EPM1270F256I5

Manufacturer Part Number
EPM1270F256I5
Description
IC MAX II CPLD 1270 LE 256-FBGA
Manufacturer
Altera
Series
MAX® IIr
Datasheets

Specifications of EPM1270F256I5

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.2ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
1270
Number Of Macrocells
980
Number Of I /o
212
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
1270
Family Name
MAX II
# Macrocells
980
Frequency (max)
1.8797GHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
127
# I/os (max)
212
Operating Supply Voltage (typ)
2.5/3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
For Use With
544-2380 - KIT DEV MAXII W/EPM 1270N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1381
EPM1270F256I5

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2–24
Figure 2–19. MAX II IOE Structure
Note to
(1) Available in EPM1270 and EPM2210 devices only.
I/O Blocks
MAX II Device Handbook
Figure
Data_in
2–19:
Fast_out
The IOEs are located in I/O blocks around the periphery of the MAX II device. There
are up to seven IOEs per row I/O block (5 maximum in the EPM240 device) and up to
four IOEs per column I/O block. Each column or row I/O block interfaces with its
adjacent LAB and MultiTrack interconnect to distribute signals throughout the device.
The row I/O blocks drive row, column, or DirectLink interconnects. The column I/O
blocks drive column interconnects.
Data_out
OE
Drive Strength Control
Programmable
Input Delay
Open-Drain Output
DEV_OE
Slew Control
Optional Schmitt
Trigger Input
Optional
PCI Clamp (1)
V
CCIO
V
CCIO
I/O Pin
Programmable
Pull-Up
© October 2008 Altera Corporation
Optional Bus-Hold
Circuit
Chapter 2: MAX II Architecture
I/O Structure

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