PPC460EX-SUB800N AMCC, PPC460EX-SUB800N Datasheet - Page 18

• Manufacturer Part Number: PPC460EX-SUB800N
• Manufacturer: AMCC

460EX – PPC460EX Embedded Processor
DMA 4-Channel Controller
The 4-channel DMA controller provides a DMA interface between the PLB memories and internal and external
peripheral devices.
Features include:
I2O/DMA Controller
The I2O/DMA controller provides one High Speed DMA (HSDMA) interface to the PLB and support for I2O
messaging. The HSDMA provides single-channel direct memory access support to ease the CPU burden. I2O
manages Message Frame Address (MFA) FIFOs or queues in memory in response to I2O register reads and
writes and transfers message frames.
DMA features include:
I2O features include:
18
• Supports the following transfers:
• Scatter/Gather capability for programming multiple DMA operations
• 8-, 16-, 32-bit peripheral support (OPB and external)
• 64-bit addressing
• 128 byte FIFO buffer
• Address increment or decrement
• Support for:
• Programmable Command Pointer FIFO and Completion FIFO size (up to 2048 DMA operations queued)
• Separate 512-byte buffering for transmit and receive
• Simultaneous fill and drain (PLB read/write pipelining)
• Any source PLB address to any destination address
• No memory alignment restrictions on source or destination
• 32-byte command descriptor block
• Maximum transfer size of 16MB
• 64-bit addressing
• Prefetch indicators for PCI buffer management
• Supports initiation of transfer to the following address spaces:
• I2O pull- and push-messaging methods
• Dynamic message frame size
• Programmable FIFO size (4096 64-bit MFAs maximum)
• 64- and 32-bit MFA sizes
• Three interrupt gathering methods
• Registered MFA prefetch and posting
• 32-bit inbound and outbound doorbell registers
• Four 32-bit scratch pad registers
– Memory-to-memory
– Buffered peripheral to memory
– Buffered memory to peripheral
– Internal and external peripherals
– Memory mapped peripherals
– Peripherals running on slower frequency buses
– 1.4GB throughput (local read)
– 1.0GB throughput (remote read)
– Single beat I/O reads and writes
– Single beat and burst memory reads and writes
– Single beat configuration reads and writes (type 0 and type 1)
– Single beat special cycles
Preliminary Data Sheet
Revision 1.19 – June 17, 2009
AMCC Proprietary