PPC460EX-SUB800N AMCC, PPC460EX-SUB800N Datasheet - Page 12

• Manufacturer Part Number: PPC460EX-SUB800N
• Manufacturer: AMCC

460EX – PPC460EX Embedded Processor
L2 Cache/SRAM
The PPC460EX also provides a 256KB L2 cache between the Processor Local Bus and the processor’s D- and
I-caches. This memory unit can be alternatively programmed to function as 256KB of SRAM.
Features include:
On-Chip Memory (OCM)
The PPC460EX provides 64KB of on-chip memory.
Features include:
Internal Buses
The PowerPC 460EX features four standard internal buses: one Processor Local Bus (PLB), one On-chip
Peripheral Bus (OPB), the Advanced High-performance Bus (AHB), and the Device Control Register bus (DCR).
The high performance, high bandwidth functions such as the PowerPC 440 processor, the DDR SDRAM memory
controller, PCI Express, PCI, and the AHB bridge, connect to the PLB. The OPB hosts lower data rate peripherals.
The daisy-chained DCR provides a lower bandwidth path for passing status and control information between the
processor and the other on-chip cores.
The PLB has a Crossbar arbiter that supports data transfer between the PLB master and two slave segments
identified as the Low Latency (LL) and High Bandwidth (HB) segments. The LL segment allows PLB masters CPU
and I2O, that are adversely affected by latency, to communicate with slave devices with minimal latency. The HB
segment allows PLB masters DMA, PCI and PCI Express to exchange large blocks of data with SDRAM, PCI and
PCI Express without interfering with the low latency PLB masters.
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• Four banks of 64KB each
• Memory cycles supported:
• Sustainable 3.2GB/s peak bandwidth at 200MHz
• Use as an L2 cache improves processor performance and reduces the PLB load
• Up to 128-bit bus width
• 128-bit slave attachment, addressable by any PLB master
• Transfers by PLB slave cycles:
• Guarded memory access on 4KB boundaries
• Data parity checking
• Data transfers at PLB bus speeds
• Power management
• Use as storage area for DMA descriptors and packet data for processing by Ethernet and Security Function.
– Single beat read and write, 1 to 16 bytes
– Quadword Read and Write burst for 12-bit master
– Guarded memory accesses on 4KB boundaries
– Cache coherency maintained by a hardware snoop mechanism on the Low Latency (LL) Processor Local
– Data Array and Tag Array parity
– Unified data and instruction cache
– Four-way set associative
– 36-bit addressing
– Full LRU replacement algorithm
– Write through, look aside
– Single-beat read and write (1 to 8 bytes for 64-bit masters, 1 to 16 bytes for 128-bit masters)
– 4- and 8-word line reads and writes
– Double word read and write bursts for 64-bit masters
– Quadword read and write bursts for 128-bit masters
– Slave-terminated double word and quadword fixed length bursts
– Master-terminated variable length bursts
Bus (PLB) or by software
Preliminary Data Sheet
Revision 1.19 – June 17, 2009
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