PPC460EX-SUB800N AMCC, PPC460EX-SUB800N Datasheet - Page 66
PPC460EX-SUB800N
Manufacturer Part Number
PPC460EX-SUB800N
Description
Manufacturer
AMCC
Datasheet
1.PPC460EX-SUB800N.pdf
(106 pages)
- Current page: 66 of 106
- Download datasheet (2Mb)
460EX – PPC460EX Embedded Processor
Table 9. Signal Functional Description (Part 3 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OV
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OV
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OV
66
DDR2/1 SDRAM Interface
BA0:2
BankSel0:3
CAS
ClkEn0:3
DM0:7
DM8
DQS0:7
DQS0:7
DQS8
DQS8
ECC0:7
MemAddr00:14
MemData00:63
MemClkOut0:1
MemClkOut0:1
MemODT0:3
RAS
WE
MemVRef1A:B
MemVRef2A:B
MemDCFdbkD
MemDCFdbkR
HISRRst
GND) required
Signal Name
Bank Address supporting up to eight internal banks.
Selects up to four external DDR SDRAM banks (a.k.a. ranks).
Column Address Strobe.
Clock Enable.
Memory write data byte lane masks. DM8 is the byte lane mask
for the ECC byte lane.
Differential byte lane data strobe.
Differential byte lane data strobe for ECC.
ECC check bits 0:7.
Memory address bus.
MemAddr14 is the most significant bit (msb).
Memory data bus (MemData32:63 available for DDR2 only).
MemData00 is the most significant bit (msb).
Subsystem clock outputs.
DDR2 On-die termination enable (not used with DDR1).
Row Address Strobe.
Write Enable.
Memory voltage reference 1, A and B input.
Memory voltage reference 2, A and B input.
Feedback driver for I/O timing measurements.
Note: Connect directly to MemDCFdbkR. Use the shortest trace
length possible. Do not include series termination or parallel
termination to Vtt.
Feedback receiver. Connect externally to MemDCFdbkD.
SDRAM hardware initiated self-refresh reset control.
DD
or 8.2kΩ for PCI to OV
Description
DD
DD
) or pull-down (recommended value is 1kΩ to
or equivalent.
Preliminary Data Sheet
DD
Revision 1.19 – June 17, 2009
or equivalent.
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
Volt ref receiver
(1.25V or 0.9V)
(1.25V or 0.9V)
SSTL2 Dr/Rcv
SSTL2 Dr/Rcv
SSTL2 Dr/Rcv
SSTL2 Dr/Rcv
SSTL2 Dr/Rcv
SSTL2 Dr/Rcv
SSTL2 Dr/Rcv
SSTL2 Dr/Rcv
SSTL2 Dr/Rcv
SSTL2 Dr/Rcv
SSTL2 Dr/Rcv
SSTL2 Dr/Rcv
SSTL2 Dr/Rcv
SSTL2 Dr/Rcv
Volt ref driver
3.3V LVTTL
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
SSTL2 Diff
Diff Driver
Dr/Rcv
Type
AMCC Proprietary
Notes
1, 2
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