PPC460EX-SUB800N AMCC, PPC460EX-SUB800N Datasheet - Page 14

• Manufacturer Part Number: PPC460EX-SUB800N
• Manufacturer: AMCC

460EX – PPC460EX Embedded Processor
PCI Controller
The PCI interface allows connection of PCI devices to the PowerPC processor and local memory. This interface is
designed to Version 2.3 of the PCI Specification and supports 32- bit PCI devices.
Reference Specifications:
Features include:
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• SGT features:
• IPsec/SSL security acceleration engine
• DES, 3DES, AES, ARC-4 encryption (no support for hashing of zero length messages)
• MD-5, SHA-1, and SHA-2 (224-, 256-, 384-, and 512-bit) hashing, HMAC encrypt-hash and hash-decrypt
• Public key acceleration (PKA) for RSA, DSA and Diffie-Hellman
• True (TRNG) or pseudo (PRNG) random number generators
• Interrupt controller
• DMA controller
• PCI Specification Version 2.3
• PCI Bus Power Management Interface Specification Version 1.1
• Frequency to 66MHz
• 32-bit bus
• PCI Host Bus Bridge or an Adapter Device's PCI interface
• Internal PCI arbitration function, supporting up to four external devices, that can be disabled for use with an
• Support for inbound and outbound Message Signaled Interrupts (MSI)
• Simple message passing capability
• Asynchronous to the PLB
• PCI Power Management 1.1
• PCI register set addressable both from on-chip processor and PCI device sides
• Ability to boot from PCI bus memory
• Error tracking/status
• Supports initiation of transfers of the following types:
• Vital Product Data (VPD) support
external arbiter
– GCM-AES with 128-bit key, 96-bit IV (nonce) and 128-bit ICV
– SecTAG header with or without Secure Channel Identifier (SCI) field
– Replay protection "Strict order Mode" and "Out of Order Mode"
– Header insertion and removal
– ICV generation and validation
– Non-deterministic true random numbers
– Pseudo random numbers with lengths of 8 or 16 bytes
– ANSI X9.17 Annex C compliant using a DES algorithm
– Fifteen programmable, maskable interrupts
– Initiate commands by means of an input interrupt
– Sixteen programmable interrupts indicating completion of certain operations
– All interrupts mapped to one level- or edge-sensitive programmable interrupt output
– Autonomous, 4-channel
– 1024 words (32 bits/word) per DMA transfer
– Scatter/gather capability with byte aligned addressing
– Single beat I/O reads and writes
– Single beat and burst memory reads and writes
– Single beat configuration reads and writes (type 0 and type 1)
– Single beat special cycles
Preliminary Data Sheet
Revision 1.19 – June 17, 2009
AMCC Proprietary