IDT49C466APQF IDT, Integrated Device Technology Inc, IDT49C466APQF Datasheet - Page 9

• Manufacturer Part Number: IDT49C466APQF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT49C466APQF

• Lead Free Status / Rohs Status: Not Compliant

R/W FIFO Operation At Boundaries
Similarly the read pointer is incremented on every FIFO read. In most cases
on a FIFO read, the last data read remains at the output of the FIFO, until
the read pointer is further incremented. On the last (the write that fills the
FIFO) FIFO write after the FIFO read, however, this last read data is
overwritten by the 16th write following the empty condition and consequently
the data at the FIFO output is liable to change. The situation is depicted in
the diagram below.
through a sequence of write operations. After the first write, a read is
executed which establishes the data at the FIFO output(AA). On the last write
to the FIFO(the write that fills the FIFO), the location of the last read data is
overwritten and the FIFO output changes from AA to the data just written,
namely QQ.
IDT49C466, IDT49C466A
64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
In the 49C466 the write pointer is incremented on every FIFO write.
The diagram in figure 2 progresses from the FIFO initialization(reset)
(data = QQ )
(data = CC)
(data = PP)
(data = BB)
(data = AA)
W RITE16
W RITE15
W RITE2
W RITE1
W RITE1
reset
Figure 2. R/W FIFO Operation
RP
RP
W P
W P
RP
RP
RP
RP
RP
W P
W P
W P
W P
(em pty)
W P
(em pty)
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
(full)
9
In case of a burst operation where FIFO data is output at a much slower rate
than the rate at which data is input and the full flag is expected to inhibit further
writes, the user cannot expect the FIFO output to remain static through the
16th write of the burst. If this is a requisite to the design, the FIFO output should
be latched. In the case of the write FIFO this can be accomplished on-chip
by latching the FIFO output in the SD output latch. For the read FIFO, the
FIFO output must be latched externally to accomplish the same thing, since
there is no latch on-chip following the FIFO. If this cannot be done and the
situation described above is expected to occur in normal operation, the write
must be inhibited one cycle before the FIFO becomes full.
This operation needs to be taken into account in the design of the system.
(data = Q Q)
(data = AA)
(data = AA)
(data = AA)
No READ s
No READ s
No READ s
No R EAD s
(data = AA)
READ1
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