IDT49C466APQF IDT, Integrated Device Technology Inc, IDT49C466APQF Datasheet - Page 4

• Manufacturer Part Number: IDT49C466APQF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT49C466APQF

• Lead Free Status / Rohs Status: Not Compliant

PIN DESCRIPTION
IDT49C466, IDT49C466A
64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
Data Buses
SD
MD
CBI
CBSYN
P
Control Inputs
SOE
BE
MOE
MDILE
MDOLE
SDOLE
SDILE
WBSEL
WBEN
WBREN
RS
0-7
0-63
0-7
0-1
Pin Name
0-63
0-7
0-7
I/O
I/O
I/O
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
System Data Bus: is a bidirectional 64-bit bus interfacing to the system or CPU. When System Output Enable, SOE,
is HIGH or Byte Enable, BE
BE
Memory Data Bus: is a bidirectional 64-bit bus interfacing to the memory. During a read cycle, (MOE HIGH) memory data
is input for error detection and correction. Data is output on the Memory Data Bus, when MOE is LOW.
Check Bit Inputs: interface to the check bit memory.
Check Bit/Syndrome Output: when MOE is LOW, the generated check bits are output. When CBSEL is HIGH and MOE
is HIGH, the syndrome bits are output. The bus is tristated when MOE = 1 and CBSEL = 0.
Parity for bytes 0 to 7: these pins are parity inputs when the corresponding Byte Enable (BE) is LOW or SOE is HIGH,
and are used to generate the parity error signal (PERR). These pins are outputs when the corresponding Byte Enable (BE)
is HIGH and SOE is LOW.
System Output Enable: enables system data bus output drivers if the corresponding Byte Enable (BE
Byte Enable: is used along with SOE to enable the System Data outputs for a particular byte. For example, if BE
the System data outputs for byte 1 (SD
HIGH during a memory read cycle, that byte is fed back to the memory data bus. This is used during partial word write
operations and writing corrected data back to memory.
Memory Output Enable: when LOW, enables the output buffers of the memory data bus (MD) and CBSYN bus. It also
controls the CBSYN mux. When LOW, checkbits are selected, when HIGH, syndrome is selected.
Memory Data Input Latch Enable: on the HIGH-to-LOW transition, latches MD and CBI in MD input latch and MD check
bit latch respectively. The latches are transparent when MDILE is HIGH.
Memory Data Output Latch Enable: latches data in the MD output latch on the LOW-to-HIGH transition of MDOLE. When
MDOLE is LOW, the MD output latch is transparent.
System Data Output Latch Enable: latches data in the SD output latch and the SD checkbit latch on the LOW-to-HIGH
transition of SDOLE. The latch is transparent when SDOLE is LOW.
System Data Input Latch Enable: latches SD in the SD input latch on the HIGH-to-LOW transition. When SDILE is HIGH,
the SD input latch is transparent.
Write FIFO Select: when HIGH, the write FIFO is selected. When WBSEL is LOW, the SD input latch is selected.
Write FIFO Enable: when LOW, allows SD data to be written to the write FIFO on the SCLK rising edge.
Write FIFO Read Enable: when LOW, allows data to be read from the the write FIFO on MCLK rising edge.
Reset and Select pins (read and write FIFO FIFOs)
0-7
, is HIGH, the SD bus output drivers are enabled.
RS
0
0
1
1
1
RS
0
1
0
1
0
0-7
, is LOW, data can be input. When System Output Enable, SOE, is LOW and Byte Enable,
Function
Reset 16-deep FIFO or first 8-deep FIFO
Reset second 8-deep FIFO
Select 16-deep FIFO or first 8-deep FIFO
Select second 8-deep FIFO
4
8-15
) are enabled. The BE
Description
0-7
pins also control the byte mux. If a particular BE is
COMMERCIAL TEMPERATURE RANGE
0-7
) is HIGH.
1
is HIGH,