ADWPCIXRSKU20 Intel, ADWPCIXRSKU20 Datasheet - Page 41

• Manufacturer Part Number: ADWPCIXRSKU20
• Manufacturer: Intel

Specifications of ADWPCIXRSKU20

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel® Server Board SE7320VP2
supported frequency of that card. When populating add-in cards in the PCI-X riser card, the
add-in cards must be installed starting with the bottom PCI slot. A second add-in card must be
installed in the middle slot, and so on. These population rules must be followed to maintain the
signal integrity of the bus.
When configured with a riser card supporting PCI Express technology, the full-height riser can
support either one x4 PCI Express card, in the 1U riser card or one x4 PCI Express card and
one PCI-X card, in the 2U riser card. The top PCI Express slot in the 2U riser card is not usable
by the Server Board SE7320VP2. The maximum supported bus speed is 66MHz with the 2U
riser card with the PCI-X slot. Population rules are similar to those of the PCI-X risers. These
population rules must be followed to maintain the signal integrity of the bus.
3.4.1.6
The BIOS assigns PCI bus numbers in a depth-first hierarchy, in accordance with the PCI Local
Bus Specification. When a bridge device is located, the bus number is incremented in exception
of a bridge device in the chipsets. Scanning continues on the secondary side of the bridge until
all subordinate buses are defined. PCI bus numbers may change when PCI-PCI bridges are
added or removed. If a bridge is inserted in a PCI bus, all subsequent PCI bus numbers below
the current bus are increased by one.
3.4.1.7
PCI configuration space protocol requires that all PCI buses in a system be assigned a bus
number. Bus numbers must be assigned in ascending order within hierarchical buses. Each PCI
bridge has registers containing its PCI bus number and subordinate PCI bus number, which
must be loaded by POST code. The subordinate PCI bus number is the bus number of the last
hierarchical PCI bus under the current bridge. The PCI bus number and the subordinate PCI
bus number are the same in the last hierarchical bridge.
3.4.1.8
Each device under a PCI bridge has its IDSEL input connected to one bit out of the PCI bus
address/data signals AD[31::11] for the PCI bus. Each IDSEL-mapped AD bit acts as a chip
select for each device on PCI. The host bridge responds to a unique PCI device ID value that,
along with the bus number, cause the assertion of IDSEL for a particular device during
configuration cycles. The following table shows the correspondence between IDSEL values and
PCI device numbers for the PCI bus. The lower five bits of the device number are used in
CONFIG_ADDRESS bits [15::11].
Revision 2.1
MCH host-HI bridge/DRAM controller
MCH DRAM Controller Error Reporting
MCH DMA controller
MCH EXP Bridge A0
MCH EXP Bridge A1
MCH EXP Bridge B0
MCH EXP Bridge B1
Scan Order
PCI Bus Numbering
Device Number and IDSEL Mapping
Table 9. PCI Configuration IDs and Device Numbers
PCI Device
Intel order number C91056-002
IDSEL
00 / 00 / 0
00/00/1
00/01/00
00/02/00
00/03/00
00/04/00
00/05/00
Bus# / Device# / Function#
Functional Architecture
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