ADWPCIXRSKU20 Intel, ADWPCIXRSKU20 Datasheet - Page 27

• Manufacturer Part Number: ADWPCIXRSKU20
• Manufacturer: Intel

Specifications of ADWPCIXRSKU20

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel® Server Board SE7320VP2
3.2
The architecture of the Server Board SE7320VP2 is designed around the Intel
The chipset consists of two components that together are responsible for providing the interface
between all major sub-systems on the baseboard, including the processor, memory, and I/O
sub-systems. These two components are:
The following sub-sections describe the primary functions and supported features of each
chipset component as they are used on the Server Board SE7320VP2. Later sections provide
more detail on the implementation of the sub-systems.
3.2.1
The MCH integrates four functions into a single 1077-ball FC-BGA package:
3.2.1.1
The E7320 MCH supports either single or dual processor configurations using 800MHz FSB
Intel
address and request interface is double pumped to 400 MHz while the 64-bit data interface
(+ parity) is quad pumped to 800 MHz. This provides a matched system bus address and data
bandwidths of 6.4 GB/s
3.2.1.2
The MCH provides an integrated memory controller for direct connection to two channels of
registered DDR-266, DDR-333, or DDR2-400 memory (stacked or unstacked). Peak theoretical
memory data bandwidth using DDR-266 technology is 4.26 GB/s and 5.33 GB/S for DDR-333
technology. For DDR2-400 technology, this increases to 6.4 GB/s.
Several RASUM (Reliability, Availability, Serviceability, Usability and Manageability) features
are provided by the E7320 MCH memory interface:
Revision 2.1
®
Xeon™ processors. The MCH supports a base system bus frequency of 200 MHz. The
Intel
Memory Controller Hub (E7320 MCH)
I/O Controller Hub (6300ESB ICH)
Front Side Bus
Memory Controller
PCI Express Controller
Hub Link Interface
DIMM sparing allows one DIMM per channel to be held in reserve and brought on-line if
another DIMM in the channel becomes defective.
Hardware periodic memory scrubbing, including demand scrub support.
Retry on uncorrectable memory errors.
x4 SDDC for memory error detection and correction of any number of bit failures in a
single x4 memory device.
®
E7320 Memory Controller Hub (MCH)
Front Side Bus (FSB)
MCH Memory Sub-System Overview
E7320 chipset
Intel order number C91056-002
Functional Architecture
®
E7320 chipset.
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