ADWPCIXRSKU20 Intel, ADWPCIXRSKU20 Datasheet - Page 37

• Manufacturer Part Number: ADWPCIXRSKU20
• Manufacturer: Intel

Specifications of ADWPCIXRSKU20

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel® Server Board SE7320VP2
mechanism, which provides x4 SDDC protection for DIMMS that utilize x4 devices. Bits from x4
parts are presented in an interleaved fashion such that each bit from a particular part is
represented in a different ECC word. DIMMs that use x8 devices, can use the same algorithm
but will not have x4 SDDC protection, since at most only four bits can be corrected with this
method. The algorithm does provide enhanced protection for the x8 parts over a standard SEC-
DED implementation. With two memory channels, either ECC method can be utilized with equal
performance, although single-channel mode only supports standard SEC/DED.
3.3.6.2
The Intel E7320 MCH includes an integrated engine to walk the populated memory space
proactively seeking out soft errors in the memory subsystem. In the case of a single bit
correctable error, this hardware detects, logs, and corrects the data except when an incoming
write to the same memory address is detected. For any uncorrectable errors detected, the scrub
engine logs the failure. Both types of errors may be reported via multiple alternate mechanisms
under configuration control. The scrub hardware will also execute “demand scrub” writes when
correctable errors are encountered during normal operation (on demand reads, rather than
scrub-initiated reads). This functionality provides incremental protection against time-based
deterioration of soft memory errors from correctable to uncorrectable.
Using this method, a 16GB system can be completely scrubbed in less than one day. The effect
of the scrub writes do not cause any noticeable degradation to memory bandwidth, although
they will cause a greater latency for that one very infrequent read that is delayed due to the
scrub write cycle.
An uncorrectable error encountered by the memory scrub engine is a “speculative error.” This
designation is applied because no system agent has specifically requested use of the corrupt
data, and no real error condition exists in the system until that occurs. It is possible that the
error resides in an unmodified page of memory that will be simply dropped on a swap back to
disk. Were that to occur, the speculative error would simply “vanish” from the system
undetected without adverse consequences.
3.3.6.3
The Intel E7320 MCH includes specialized hardware to resubmit a memory read request upon
detection of an uncorrectable error. When a demand fetch (as opposed to a scrub) of memory
encounters an uncorrectable error as determined by the enabled ECC algorithm, the memory
control hardware will cause a (single) full resubmission of the entire cache line request from
memory to verify the existence of corrupt data. This feature is expected to greatly reduce or
eliminate the reporting of false or transient uncorrectable errors in the DRAM array.
Any given read request will only be retried once on behalf of this error detection mechanism. If
the uncorrectable error is repeated, it will be logged and escalated as directed by device
configuration.
3.3.6.4
The Intel E7320 MCH provides hardware managed ECC auto-initialization of all populated
DRAM space under software control. Once internal configuration has been updated to reflect
the types and sizes of populated DIMM devices, the MCH will traverse the populated address
space initializing all locations with good ECC. This not only speeds the mandatory memory
Revision 2.1
Integrated Memory Scrub Engine
Retry on Uncorrectable Error
Integrated Memory Initialization Engine
Intel order number C91056-002
Functional Architecture
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