UTOPIA16EVK/NOPB National Semiconductor, UTOPIA16EVK/NOPB Datasheet - Page 82

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UTOPIA16EVK/NOPB

Manufacturer Part Number
UTOPIA16EVK/NOPB
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of UTOPIA16EVK/NOPB

Lead Free Status / Rohs Status
Compliant
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U_UDBClk,
U_UUBClk
U_TxData[15:0],
U_TxPrty,
U_TxSOC,
U_TxEnb[7:0],
U_TxAddr[4:0]
U_TxClav [7:0]
U_UDBClk,
U_UUBClk
U_RxData[15:0],
U_RxParity,
U_RxSOC,
U_RxClav [7:0]
24.0 Electrical Characteristics
U_RxEnb[7:0],
U_RxAddr[4:0]
Signal Name
Signal Name
A → P
A → P
A ← P
A → P
A → P
A ← P
DIR
DIR
Item
tT10
tT12
Item
tT10
tT12
tT11
tT11
tT2
tT3
tT4
tT5
tT6
tT7
tT8
tT9
tT2
tT3
tT4
tT5
tT6
tT7
tT8
tT9
f1
f1
TABLE 97. UTOPIA Transmit Timing
TABLE 98. UTOPIA Receive Timing
TxClk Frequency (nominal)
TxClk Duty Cycle
TxClk Peak-to-Peak Jitter
TxClk Rise/Fall Time
Input Setup to TxClk
Input Hold from TxClk
Input Setup to TxClk
Input Hold from TxClk
Signal Going Low Impedance to TxClk
Signal Going High Impedance to
TxClk (1)
Signal Going Low Impedance from
TxClk
Signal Going High Impedance from
TxClk
RxClk Frequency (nominal)
RxClk Duty Cycle
RxClk Peak-to-Peak Jitter
RxClk Rise/Fall Time
Input Setup to RxClk
Input Hold from RxClk
Input Setup to RxClk
Input Hold from RxClk
Signal Going Low Impedance to
RxClk
Signal Going High Impedance to
RxClk (2)
Signal Going Low Impedance from
RxClk
Signal Going High Impedance from
RxClk
(Continued)
Description
Description
82
40%
4 ns
1 ns
4 ns
1 ns
4 ns
0 ns
1 ns
1 ns
40%
4 ns
1 ns
4 ns
1 ns
4 ns
0 ns
1 ns
1 ns
Min
Min
0
0
50 MHz
50 MHz
60%
60%
Max
2 ns
Max
2 ns
5%
5%