UTOPIA16EVK/NOPB National Semiconductor, UTOPIA16EVK/NOPB Datasheet - Page 17

• Manufacturer Part Number: UTOPIA16EVK/NOPB
• Manufacturer: National Semiconductor

Specifications of UTOPIA16EVK/NOPB

• Lead Free Status / Rohs Status: Compliant

8.0 UTOPIA Interface Operation
port address of 0 and a sub-port address of 7 means that the
destination PHY is MPhy address 0 attached to U_TxENB[7]
and U_TxCLAV[7]. The cell is then transmitted to that PHY.
Receive Path Example: The DS92UT16 in ATM mode re-
ceives a cell from the PHY with MPhy address 0 attached to
U_RxENB[6] and U_RxCLAV[6] and designates it as from
Port 0 Sub-Port 6. The DS92UT16 inserts the sub-port ad-
dress 6 (binary “110”) into the sub-port address location of
the received PDU. Then this PDU is transmitted to the
head-end. The head-end ATM layer device must extract this
sub-port address from the PDU to determine the full address
of the originating PHY.
(Continued)
FIGURE 10. Sub-Port Address Operation
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8.2.4 Connected Port and Sub-Port Lists
Figure 11 illustrates the usage of the connected port list
registers (UCPL3–UCPL0) and the connected sub-port list
register (UCSPL). In this case, the DS92UT16 in ATM mode
defines Port 1 and Sub-port 7 as not connected.
The UCPL3–UCPL0 registers contain 31 bits corresponding
to the 31 possible Ports addressed by the MPhy address
busses. If a bit location in the UCPL3–UCPL0 registers is
set, then that Port is connected. The sub-ports of the con-
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