UTOPIA16EVK/NOPB National Semiconductor, UTOPIA16EVK/NOPB Datasheet - Page 38

• Manufacturer Part Number: UTOPIA16EVK/NOPB
• Manufacturer: National Semiconductor

Specifications of UTOPIA16EVK/NOPB

• Lead Free Status / Rohs Status: Compliant

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17.0 Microprocessor Interface Operation
Note 6: “Cycle” must be greater than or equal to the cycle time of the slowest DS92UT16 clock.
Note 7: When an LVDS receiver loses or gains “lock”, the recovered clock may stay high for up to 2.5 cycles. If a processor access is in progress to one of the
registers in either of the recovered clock domains, then a READ will return the value of the last READ access, and a WRITE will not change the value of the target
register. To accommodate this possible gap in the clock, 3 cycles has been added to these timings and they should therefore be regarded as worst case. If access
time needs to be increased and a system is robust enough to accept these possible incorrect accesses then 3 cycles can be removed from these timings.
Note 8: A recovery time of 1 cycle is required between successive processor accesses.
SOFTWARE LOCK
Note that the device has a software lock mechanism imple-
mented for security. This is described in Section 6.5 CPU
No.
10
11
1
2
3
4
5
6
7
8
9
Address Setup Time before Chip Select Low
Chip Select Setup before Data Strobe Low
Read/Write Setup before Data Strobe Low
Data Strobe Pulse Width (Notes 6, 7)
Data Strobe Low to Data Low Impedance
Data Strobe Low to Valid Data (Notes 6, 7)
Data Strobe High to Data High Impedance
Read/Write Hold after Data Strobe High
Chip Select Hold after Data Strobe High
Address Hold after Data Strobe High
Data Strobe Recovery Time (Notes 6, 8)
Parameter
FIGURE 22. Motorola Read Cycle
TABLE 19. Motorola Read
38
INTERFACE and Section 18.1 SOFTWARE LOCK — 0x00
to 0x01 SLK0 to SLK1.
(Continued)
8 cycles
1 cycle
Min
0
0
5
5
5
0
7 cycles + 15 ns
Max
10
15
20031621
Units
ns
ns
ns
ns
ns
ns
ns
ns