UTOPIA16EVK/NOPB National Semiconductor, UTOPIA16EVK/NOPB Datasheet - Page 72

• Manufacturer Part Number: UTOPIA16EVK/NOPB
• Manufacturer: National Semiconductor

Specifications of UTOPIA16EVK/NOPB

• Lead Free Status / Rohs Status: Compliant

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N8
K1
K13
P10
A1
A11
D10
F7
F8
G2
G6
G7
G14
J7
J11
H6
H5
K2
J6
E9
E8
F12
E13
E10
C1
A14
A13
A9
A10
C14
E14
B10
D14
D2
A3
A4
A6
A7
C3
B1
D4
B2
E4
D1
D3
G8
J8
K8
20.0 Package
Ball
DGND
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
GPIO [0]
GPIO [1]
GPIO [2]
GPIO [3]
JTAG_CLK
JTAG_Reset
JTAG_TDI
JTAG_TDO
JTAG_TMS
LVDS_ADen
LVDS_ADin[−]
LVDS_ADin[+]
LVDS_ADout[−]
LVDS_ADout[+]
LVDS_ALock_n
LVDS_APwdn
LVDS_ARefClk
LVDS_ARxClk
LVDS_BDen
LVDS_BDin[−]
LVDS_BDin[+]
LVDS_BDout[−]
LVDS_BDout[+]
LVDS_BLock_n
LVDS_BPwdn
LVDS_BRefClk
LVDS_BRxClk
LVDS_Synch
LVDS_TxClk
LVDS_TxPwdn
NC
NC
NC
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
25
25
25
33
33
33
33
33
33
33
33
33
33
33
Pin Name
(Continued)
TABLE 96. Pin Locations — BGA196 Package (Continued)
GND
2.5V
2.5V
2.5V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
BiDir LVTTL
BiDir LVTTL
BiDir LVTTL
BiDir LVTTL
Input LVTTL
Input LVTTL
Input LVTTL
Output LVTTL
Input LVTTL
Input LVTTL
Diff. Input
Diff. Input
Diff. Output
Diff. Output
Output LVTTL
Input LVTTL
Input LVTTL
Output LVTTL
Input LVTTL
Diff. Input
Diff. Input
Diff. Output
Diff. Output
Output LVTTL
Input LVTTL
Input LVTTL
Output LVTTL
Input LVTTL
Input LVTTL
Input LVTTL
Signal Type
Digital GND
V
V
V
Digital V
Digital V
Digital V
Digital V
Digital V
Digital V
Digital V
Digital V
Digital V
Digital V
Digital V
General Purpose Input and Output
General Purpose Input and Output
General Purpose Input and Output
General Purpose Input and Output
Boundary Scan Test Clock
Boundary Scan Test Circuit Reset
Boundary Scan Test Data In
Boundary Scan Test Data Out
Boundary Scan Test Mode Select
Driver Enable for Transmit A
Input for Receiver Port A
Input for Receiver Port A
Output for Driver A
Output for Driver A
Lock Signal from Receive Port A
Receive Port A and Deserializer Power Down
Reference Clock for Receiver A PLL
Recovered Clock Output from Receive Port A
Driver Enable for Transmit B
Input for Receive Port B
Input for Receive Port B
Output for Driver B
Output for Driver B
Lock Signal from Receive Port B
Receive Port B and Deserializer Power Down
Reference Clock for Receiver B PLL
Recovered Clock Output from Receive Port B
Force SYNC patterns on Transmit A and B
Reference Clock for Driving Transmission Function
Powerdown for LVDS Serializer
NO CONNECT
NO CONNECT
NO CONNECT
DD
DD
DD
72
for Core Logic
for Core Logic
for Core Logic
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
Description