UTOPIA16EVK/NOPB National Semiconductor, UTOPIA16EVK/NOPB Datasheet - Page 40

• Manufacturer Part Number: UTOPIA16EVK/NOPB
• Manufacturer: National Semiconductor

Specifications of UTOPIA16EVK/NOPB

• Lead Free Status / Rohs Status: Compliant

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RAHECC2
RAHECC1
RAHECC0
RAHECT2
RAHECT1
RAHECT0
RABIPC2
RABIPC1
RABIPC0
RABIPT2
RABIPT1
RABIPT0
RAPA
RAPIE
RARA
RARIE
RAU2DLBC
Unused
RACDT
RAFDT
RADSLKT
RABEC2
RABEC1
RABEC0
Unused
Reserved
Reserved
Unused
Resered
Reserved
Reserved
Reserved
Unused
Reserved
Reserved
Reserved
Reserved
RBLL
RBELL
RBLA
RBLIE
RBCTL
Reserved
ERBD7
ERBD6
ERBD5
Register Name
18.0 Register Description
Address
0x49 to
0x2E
0x2F
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x56
0x57
0x58
0x59
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
Software
Lock
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
N
N
N
N
N
N
N
Y
N
N
N
TABLE 20. Register Map Summary (Continued)
(Continued)
Reset
Value
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x0D
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x78
0x78
0x88
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x00
0x00
0x00
18.27 Receive Port A HEC Count 2
18.27 Receive Port A HEC Count 1
18.27 Receive Port A HEC Count 0
18.28 Receive Port A HEC Threshold 2
18.28 Receive Port A HEC Threshold 1
18.28 Receive Port A HEC Threshold 0
18.29 Receive Port A BIP Count 2
18.29 Receive Port A BIP Count 1
18.29 Receive Port A BIP Count 0
18.30 Receive Port A BIP Threshold 2
18.30 Receive Port A BIP Threshold 1
18.30 Receive Port A BIP Threshold 0
18.31 Receive Port A Performance Alarms
18.32 Receive Port A Performance Interrupt Enables
18.33 Receive Port A Remote Alarms
18.34 Receive Port A Remote Interrupt Enables
18.35 Receive Port A ATM Up2Down Loopback Cell Count
18.36 Receive Port A Cell Delineation Thresholds
18.37 Receive Port A Frame Delineation Thresholds
18.38 Receive Port a Descrambler Lock Thresholds
18.38 Receive Port A Bit Error Count 2
18.38 Receive Port A Bit Error Count 1
18.38 Receive Port A Bit Error Count 0
18.40 Receive Port B Link Label
18.41 Receive Port B Expected Link Label
18.42 Receive Port B Local Alarms
18.43 Receive Port B Local Interrupt Enables
18.44 Receive Port B Control
18.45 ECC Receive Buffer B 7
18.45 ECC Receive Buffer B 6
18.45 ECC Receive Buffer B 5
40
Section and Description