EVAL-ADV7314EB Analog Devices Inc, EVAL-ADV7314EB Datasheet - Page 71

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EVAL-ADV7314EB

Manufacturer Part Number
EVAL-ADV7314EB
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of EVAL-ADV7314EB

Lead Free Status / Rohs Status
Not Compliant
Mode 2—Master Option
(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode, the ADV7314 can generate horizontal and vertical
sync signals. A coincident low transition of both HSYNC and
VSYNC inputs indicates the start of an odd field. A VSYNC low
transition when HSYNC is high indicates the start of an even
field. The BLANK signal is optional. When the BLANK input is
disabled, the ADV7314 automatically blanks all normally blank
lines as per CCIR-624. HSYNC is output on S_HSYNC, BLANK
on S_BLANK, and VSYNC on S_VSYNC.
REV. 0
HSYNC
BLANK
VSYNC
PIXEL
DATA
HSYNC
VSYNC
BLANK
PIXEL
DATA
Figure 86. SD Timing Mode 2 Even-to-Odd Field Transition Master/Slave
Figure 87. SD Timing Mode 2 Odd-to-Even Field Transition Master/Slave
NTSC = 16
PAL = 12
NTSC = 16
PAL = 12
CLOCK/2
CLOCK/2
CLOCK/2
CLOCK/2
NTSC = 122
PAL = 132
CLOCK/2
CLOCK/2
–71–
NTSC = 122
PAL = 132
NTSC = 858
PAL = 864
Cb
CLOCK/2
CLOCK/2
CLOCK/2
CLOCK/2
Y
Cr
Y
Cb
Cb
Y
Cr
Y
ADV7314