EVAL-ADV7314EB Analog Devices Inc, EVAL-ADV7314EB Datasheet - Page 27

• Manufacturer Part Number: EVAL-ADV7314EB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADV7314EB

• Lead Free Status / Rohs Status: Not Compliant

REV. 0
SR7-
SR0 Register
4Ah SD Timing Register 0
4Bh SD Timing Register 1
4Ch SD F
4Dh SD F
4 E h SD F
4 F h SD F
5 0 h
5 1 h
5 2 h
5 3 h
5 4 h
5 5 h
5 6 h
5 7 h
5 8 h
SD F
SD Closed Captioning
SD Closed Captioning
SD Closed Captioning
SD Closed Captioning
SD Pedestal Register 0
SD Pedestal Register 1
SD Pedestal Register 2
SD Pedestal Register 3
SC
SC
SC
SC
SC
Register 0
Register 1
Register 2
Register 3
Phase
HSYNC
VSYNC
HSYNC to Pixel Data
Adjust
Bit Description
SD Slave/Master Mode
Data on Odd Fields
Data on Odd Fields
SD Timing Mode
SD BLANK Input
SD Luma Delay
SD Min. Luma Value
SD Timing Reset
SD HSYNC Width
SD HSYNC to VSYNC delay
SD HSYNC to VSYNC Rising
Edge Delay [Mode 1
only] VSYNC Width
[Mode 2 only]
Extended Data on Even
Fields
Extended Data on Even
Fields
Pedestal on Odd Fields 17
Pedestal on Odd Fields 25
Pedestal on Even Fields 17
Pedestal on Even Fields 25
t
LINE 1
B
Figure 20. Timing Register 1 in PAL Mode
t
A
Bit 7
x
0
0
1
1
x
x
x
x
x
x
x
x
x
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
0
1
0
0
1
0
1
x
x
x
x
x
x
x
x
x
16
24
16
24
0
0
1
1
0
x
x
0
0
1
1
x
x
x
x
x
x
x
x
x
15
23
15
23
–27–
0
1
0
1
0
0
1
0
1
0
1
x
x
x
x
x
x
x
x
x
14
22
14
22
0
1
0
0
0
1
1
x
x
x
x
x
x
x
x
x
13
21
13
21
0
0
1
1
0
0
1
0
1
x
x
x
x
x
x
x
x
x
12
20
12
20
t
C
0
1
0
1
0
0
0
1
1
x
x
x
x
x
x
x
x
x
11
19
11
19
LINE 313
0
1
0
0
1
0
1
x
x
x
x
x
x
x
x
x
10
18
10
18
Slave mode
Master mode
Mode 0
Mode 1
Mode 2
Mode 3
Enabled
Disabled
2 clk cycles
4 clk cycles
6 clk cycles
–40 IRE
–7.5 IRE
A low-high-low transistion will
reset the internal SD timing
counters
Ta = 1 clk cycle
Ta = 4 clk cycles
Ta = 16 clk cycles
Ta = 128 clk cycles
Tb = 0 clk cycle
Tb = 4 clk cycles
Tb = 8 clk cycles
Tb = 18 clk cycles
Tc = Tb
Tc = Tb + 32
1 clk cycle
4 clk cycles
16 clk cycles
128 clk cycles
0 clk cycles
1 clk cycle
2 clk cycles
3 clk cycles
Subcarrier Frequency Bit 7–0
Subcarrier Frequency Bit 15–8
Subcarrier Frequency Bit 23–16
Subcarrier Frequency Bit 31–24
Subcarrier Phase Bit 9–2
Extended Data Bit 7–0
Extended Data Bit 15–8
Data Bit 7–0
Data Bit 15–8
Setting any of these bits to 1 will
disable pedestal on the line
number indicated by the bit
settings.
No delay
LINE 314
s
ADV7314
Reset
Value
0 8 h
0 0 h
1 6 h
7Ch
F 0 h
2 1 h
0 0 h
0 0 h
0 0 h
0 0 h
0 0 h
0 0 h
0 0 h
0 0 h
0 0 h