EVAL-ADV7314EB Analog Devices Inc, EVAL-ADV7314EB Datasheet - Page 19

• Manufacturer Part Number: EVAL-ADV7314EB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADV7314EB

• Lead Free Status / Rohs Status: Not Compliant

REV. 0
SR7-
SR0
00h
01h
Register
Power
Mode
Register
Mode Select
Register
Bit Description
Sleep Mode. With this control enabled, the current
consumption is reduced to A level. All DACs and
the internal PLL cct are disabled. I
be read from and written to in sleep mode.
PLL and Oversampling Control. This control
allows the internal PLL cct to be powered down
and the oversampling to be switched off.
DAC F. Power on/off.
DAC E. Power on/off.
DAC D. Power on/off.
DAC C. Power on/off.
DAC B. Power on/off.
DAC A. Power on/off.
BTA T-1004 or 1362 Compatibility
Clock Edge
Reserved
Clock Align
Input Mode
Y/S Bus Swap
2
C registers can
Bit 7
0
1
0
1
Bit 6
0
1
0
0
0
0
1
1
1
1
–19–
Bit 5
0
1
0
0
1
1
0
0
1
1
Bit 4
0
1
0
1
0
1
0
1
0
1
Bit 3 Bit 2 Bit 1 Bit 0
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
Register Setting
Sleep Mode off
Sleep Mode on
PLL on
PLL off
DAC F off
DAC F on
DAC E off
DAC E on
DAC D off
DAC D on
DAC D off
DAC C on
DAC B off
DAC B on
DAC A off
DAC A on
Disabled
Enabled
Cb clocked on rising edge
Y clocked on rising edge
Must be set if the phase
delay between the two
input clocks is <9.25 ns or
>27.75 ns.
SD input only
PS input only
HDTV input only
SD and PS [20-bit]
SD and PS [10-bit]
SD and HDTV [SD
oversampled
SD and HDTV [HDTV
oversampled]
PS only [at 54 MHz]
10-bit data on S Bus
10-bit data on Y Bus
ADV7314
Register Reset
Value (Shaded)
FCh
Only for PS dual
edge clk mode
Only for PS
interleaved input at
27 MHz
38h
Only if two input
clocks are used
SD Only. 10-Bit/
20-Bit Input mode