EVAL-ADV7314EB Analog Devices Inc, EVAL-ADV7314EB Datasheet - Page 35

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EVAL-ADV7314EB

Manufacturer Part Number
EVAL-ADV7314EB
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of EVAL-ADV7314EB

Lead Free Status / Rohs Status
Not Compliant
TIMING MODES
HD Async Timing Mode
[Subaddress 10h, Bit 3,2]
For any input data that does not conform to the standards
selectable in input mode, Subaddress 01h, asynchronous tim-
ing mode can be used to interface to the ADV7314. Timing
control signals for HSYNC, VSYNC, and BLANK have to be
programmed by the user. Macrovision and programmable
REV. 0
SET ADDRESS 10h,
SET ADDRESS 10h,
ANALOG OUTPUT
BIT 6 TO 1
P_HSYNC
P_BLANK
P_VSYNC
BIT 6 TO 1
P_HSYNC
P_BLANK
P_VSYNC
CLK
Figure 28a. Async Timing Mode—Programming Input Control Signals for SMPTE 295M Compatibility
CLK
Figure 28b. Async Timing Mode—Programming Input Control Signals for Bilevel Sync Signal
81
a
a
HORIZONTAL SYNC
66
HORIZONTAL SYNC
b
b
66
c
c
243
–35–
oversampling rates are not available in async timing mode. When
using async mode, the PLL must be turned off [Subaddress
00h, Bit 1 = 1].
Figures 28a and 28b show an example of how to program the
ADV7314 to accept a different high definition standard other
than SMPTE 293M, SMPTE 274M, SMPTE 296M, or
ITU-R BT.1358. The truth table in Table V must be followed
when programming the control signals in async timing mode.
d
d
ACTIVE VIDEO
ACTIVE VIDEO
1920
ADV7314
e
PROGRAMMABLE
INPUT TIMING
ANALOG
OUTPUT
e
0
1