PCI-BOARD/S25 Altera, PCI-BOARD/S25 Datasheet - Page 66
PCI-BOARD/S25
Manufacturer Part Number
PCI-BOARD/S25
Description
Manufacturer
Altera
Datasheet
1.PCI-BOARDS25.pdf
(76 pages)
Specifications of PCI-BOARD/S25
Lead Free Status / Rohs Status
Supplier Unconfirmed
D
C
B
A
Copyright (c) 2003, Altera Corporation. All Rights Reserved.
2.5V
LAN_BEn3
LAN_BEn2
LAN_BEn1
LAN_BEn0
LAN_A0
LAN_A1
LAN_A2
LAN_A3
LAN_A4
LAN_A5
LAN_A6
LAN_A7
LAN_A8
LAN_A9
LAN_A10
LAN_A11
LAN_A12
LAN_A13
LAN_A14
LAN_RESET
LAN_AEN
LAN_ IOCHRDY
LAN_INTRQ0
LAN_LDEVn
LAN_IORn
LAN_IOWn
LAN_LOOPBACK
B1_USER_A0
B1_USER_A1
B1_USER_B0
B1_USER_B1
B1_USER_C0
B1_USER_C1
B1_USER_D0
B1_USER_D1
B1_USER_E0
B1_USER_E1
LAN_D0
5
5
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
3.3V
1
2
3
4
5
6
7
8
RN9
G3
G4
H3
H4
G1
G2
H1
H2
M4
M5
M2
M3
N3
N4
N1
N2
R3
R4
R1
R2
F5
E4
E2
E1
F3
F4
F1
F2
J3
J4
K4
K3
J2
J1
L1
K2
L2
L3
P3
P4
P1
P2
T2
T1
U2E
EP1S40F1020
10K
DIFFIO_RX45n
DIFFIO_RX45p
DIFFIO_RX46n
DIFFIO_RX46p
DIFFIO_RX47n
DIFFIO_RX47p
DIFFIO_RX48n
DIFFIO_RX48p
DIFFIO_RX49n
DIFFIO_RX49p
DIFFIO_RX50n
DIFFIO_RX50p
DIFFIO_RX51n
DIFFIO_RX51p
DIFFIO_RX52n
DIFFIO_RX52p
DIFFIO_RX53n
DIFFIO_RX53p
DIFFIO_RX54n
DIFFIO_RX54p
DIFFIO_RX55n
DIFFIO_RX55p
DIFFIO_RX56n
DIFFIO_RX56p
DIFFIO_RX57n/RDN5
DIFFIO_RX57p/RUP5
DIFFIO_RX58n
DIFFIO_RX58p
DIFFIO_RX59n
DIFFIO_RX59p
DIFFIO_RX60n
DIFFIO_RX60p
DIFFIO_RX61n
DIFFIO_RX61p
DIFFIO_RX62n
DIFFIO_RX62p
DIFFIO_RX63n
DIFFIO_RX63p
DIFFIO_RX64n
DIFFIO_RX64p
DIFFIO_RX65n
DIFFIO_RX65p
DIFFIO_RX66n
DIFFIO_RX66p
16
15
14
13
12
11
10
9
SYS_RESETn
USER_RESETn
USER_PB2
USER_PB1
B1_REQn
B1_RESETn
B1_SYS_RESETn
(3.3V LVTTL)
BANK 5
DIFFIO_TX45n
DIFFIO_TX45p
DIFFIO_TX46n
DIFFIO_TX46p
DIFFIO_TX47n
DIFFIO_TX47p
DIFFIO_TX48n
DIFFIO_TX48p
DIFFIO_TX49n
DIFFIO_TX49p
DIFFIO_TX50n
DIFFIO_TX50p
DIFFIO_TX51n
DIFFIO_TX51p
DIFFIO_TX52n
DIFFIO_TX52p
DIFFIO_TX53n
DIFFIO_TX53p
DIFFIO_TX54n
DIFFIO_TX54p
DIFFIO_TX55n
DIFFIO_TX55p
DIFFIO_TX56n
DIFFIO_TX56p
DIFFIO_TX57n
DIFFIO_TX57p
DIFFIO_TX58n
DIFFIO_TX58p
DIFFIO_TX59n
DIFFIO_TX59p
DIFFIO_TX60n
DIFFIO_TX60p
DIFFIO_TX61n
DIFFIO_TX61p
DIFFIO_TX62n
DIFFIO_TX62p
DIFFIO_TX63n
DIFFIO_TX63p
DIFFIO_TX64n
DIFFIO_TX64p
DIFFIO_TX65n
DIFFIO_TX65p
DIFFIO_TX66n
DIFFIO_TX66p
4
4
G7
G8
G6
G5
H8
H7
H5
H6
J7
J8
J5
J6
K8
K7
K5
K6
L6
L7
M6
M7
M8
M9
N10
N9
N5
N6
P9
P10
N7
N8
P6
P5
R10
R9
R5
R6
P7
P8
R7
R8
P11
N11
T11
R11
Button is intended to reset
internal Stratix logic
(analagous to a soft reset)
Button resets board and
re-loads Stratix device
from flash memory.
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
B1_REQn
B1_RESETn
B1_PWROK
B1_STOPn
B1_SMBDAT
B1_SMBCLK
B1_SYS_RESETn
Stratix Bank 2, Bank 5, Buttons
LAN_D2
LAN_D3
LAN_D4
LAN_D5
LAN_D6
LAN_D7
LAN_D8
LAN_D9
LAN_D10
LAN_D11
LAN_D12
LAN_D13
LAN_D14
LAN_D15
LAN_D16
LAN_D17
LAN_D18
LAN_D19
LAN_D20
LAN_D21
LAN_D22
LAN_D23
LAN_D24
LAN_D25
LAN_D26
LAN_D27
LAN_D28
LAN_D29
LAN_D30
LAN_D31
LAN_D1
USER_RESETn
SYS_RESETn
2
2
PB
PB
PB1
PB3
1
1
SCRUZ_IO0
SCRUZ_IO1
SCRUZ_IO2
MICTOR_DO15
MICTOR_DO14
MICTOR_DO13
MICTOR_DO12
MICTOR_DO11
MICTOR_DO10
MICTOR_DO9
MICTOR_DO8
MICTOR_DO7
MICTOR_DO6
MICTOR_DO5
MICTOR_DO4
MICTOR_DO3
MICTOR_DO2
MICTOR_DO1
MICTOR_DO0
MICTOR_DE15
MICTOR_DE14
MICTOR_DE13
MICTOR_DE12
MICTOR_DE11
MICTOR_DE10
MICTOR_DE9
MICTOR_DE8
MICTOR_DE7
MICTOR_DE6
MICTOR_DE5
MICTOR_DE4
MICTOR_DE3
MICTOR_DE2
MICTOR_DE1
MICTOR_DE0
MICTOR_CLKO
MICTOR_CLKE
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
3
3
1
1
PB2
PB
PB4
PB
M30
M31
M29
M28
R29
R30
R31
R32
P32
P31
P30
P29
N32
N31
N30
N29
K31
K29
K30
H32
H31
G32
G31
H29
H30
G30
G29
E31
E32
E29
T31
T32
L31
L30
L32
J31
J32
J30
J29
F32
F31
F30
F29
F28
U2B
EP1S40F1020
DIFFIO_RX23n
DIFFIO_RX23p
DIFFIO_RX24n
DIFFIO_RX24p
DIFFIO_RX25n
DIFFIO_RX25p
DIFFIO_RX26n
DIFFIO_RX26p
DIFFIO_RX27n
DIFFIO_RX27p
DIFFIO_RX28n
DIFFIO_RX28p
DIFFIO_RX29n
DIFFIO_RX29p
DIFFIO_RX30n
DIFFIO_RX30p
DIFFIO_RX31n
DIFFIO_RX31p
DIFFIO_RX32n/RDN2
DIFFIO_RX32p/RUP2
DIFFIO_RX33n
DIFFIO_RX33p
DIFFIO_RX34n
DIFFIO_RX34p
DIFFIO_RX35n
DIFFIO_RX35p
DIFFIO_RX36n
DIFFIO_RX36p
DIFFIO_RX37n
DIFFIO_RX37p
DIFFIO_RX38n
DIFFIO_RX38p
DIFFIO_RX39n
DIFFIO_RX39p
DIFFIO_RX40n
DIFFIO_RX40p
DIFFIO_RX41n
DIFFIO_RX41p
DIFFIO_RX42n
DIFFIO_RX42p
DIFFIO_RX43n
DIFFIO_RX43p
DIFFIO_RX44n
DIFFIO_RX44p
2
2
Two user-defined
pushbuttons for any
use.
USER_PB1
USER_PB2
(3.3V LVTTL)
BANK 2
DIFFIO_TX23n
DIFFIO_TX23p
DIFFIO_TX24n
DIFFIO_TX24p
DIFFIO_TX25n
DIFFIO_TX25p
DIFFIO_TX26n
DIFFIO_TX26p
DIFFIO_TX27n
DIFFIO_TX27p
DIFFIO_TX28n
DIFFIO_TX28p
DIFFIO_TX29n
DIFFIO_TX29p
DIFFIO_TX30n
DIFFIO_TX30p
DIFFIO_TX31n
DIFFIO_TX31p
DIFFIO_TX32n
DIFFIO_TX32p
DIFFIO_TX33n
DIFFIO_TX33p
DIFFIO_TX34n
DIFFIO_TX34p
DIFFIO_TX35n
DIFFIO_TX35p
DIFFIO_TX36n
DIFFIO_TX36p
DIFFIO_TX37n
DIFFIO_TX37p
DIFFIO_TX38n
DIFFIO_TX38p
DIFFIO_TX39n
DIFFIO_TX39p
DIFFIO_TX40n
DIFFIO_TX40p
DIFFIO_TX41n
DIFFIO_TX41p
DIFFIO_TX42n
DIFFIO_TX42p
DIFFIO_TX43n
DIFFIO_TX43p
DIFFIO_TX44n
DIFFIO_TX44p
P22
N22
M22
M23
R26
R25
R24
R23
P26
P25
R27
R28
P27
P28
N26
N25
P24
P23
N28
N27
N23
N24
M25
M24
M27
M26
L26
L27
K25
K26
K27
K28
J26
J25
H26
H25
J28
J27
H27
H28
G27
G28
G26
G25
2
2
14
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
SCRUZ_IO3
SCRUZ_IO4
SCRUZ_IO5
SCRUZ_IO6
SCRUZ_IO7
SCRUZ_IO8
SCRUZ_IO9
SCRUZ_IO10
SCRUZ_IO11
SCRUZ_IO12
SCRUZ_IO13
SCRUZ_IO14
SCRUZ_IO15
SCRUZ_IO16
SCRUZ_IO17
SCRUZ_IO18
SCRUZ_IO19
SCRUZ_IO20
SCRUZ_IO21
SCRUZ_IO22
SCRUZ_IO23
SCRUZ_IO24
SCRUZ_IO25
SCRUZ_IO26
SCRUZ_IO27
SCRUZ_IO28
SCRUZ_IO29
SCRUZ_IO30
SCRUZ_IO31
SCRUZ_IO32
SCRUZ_IO33
SCRUZ_IO34
SCRUZ_IO35
SCRUZ_IO36
SCRUZ_IO37
SCRUZ_IO38
SCRUZ_IO39
SCRUZ_CARDSELn
Title
Size
Date:
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Stratix PCI Development Board
B
Document Number
Wednesday, February 12, 2003
5,14,17
5,17
5,17
5,17
10,17
10,17
14
14
14
14
HSDI CONTROL SIGNALS (TTL)
USER_PB[2..1]
SYS_RESETn
USER_RESETn
CPLD_USER[1..0]
14
13
13
13
13
13
13
13
13
13
13
13
10
10
10
10
10
10
10
10
10
10
HSDI USER DEFINED SIGNALS
MICTOR_DE[15..0]
MICTOR_DO[15..0]
MICTOR_CLKO
MICTOR_CLKE
SCRUZ_IO[39..0]
LAN_D[31..0]
LAN_A[14..0]
LAN_BEn[3..0]
LAN_RESET
LAN_INTRQ0
LAN_AEN
LAN_IORn
LAN_IOWn
LAN_IOCHRDY
LAN_LDEVn
LAN_LOOPBACK
B1_STOPn
B1_REQn
B1_RESETn
B1_PWROK
B1_SYS_RESETn
B1_SMBCLK
B1_SMBDAT
B1_USER_A[1..0]
B1_USER_B[1..0]
B1_USER_C[1..0]
B1_USER_D[1..0]
B1_USER_E[1..0]
150-0216200-01
Sheet
1
1
8
o f
18
R e v
B
D
C
B
A