PCI-BOARD/S25 Altera, PCI-BOARD/S25 Datasheet

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... Components Altera Corporation DS-PCIDVBD-2.0 PCI Development Kit, Stratix Edition (ordering code PCI-BOARD/S25). This data sheet refers to the board shipped with this kit as the Starter Board. PCI High-Speed Development Kit, Stratix Professional Edition (ordering code PCI-BOARD/S60). This data sheet refers to the board shipped with this kit as the Professional Board ...

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... Stratix PCI Development Board Data Sheet Expansion Interfaces Debugging Interfaces Handling the Observe the following precautions when handling the board. Board Flexible clocking options – Socketed 33-MHz system clock oscillator – Socketed 100-MHz high-speed clock oscillator – SMA connector clock input ...

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... Back) Note to Figure 1: (1) These features are only available on the Professional Board. Altera Corporation ® Megafunction Partners Program (AMPP shows a top view of the Stratix PCI development board. Configuration Done LED (D4) System Reset (PB3) User LEDs (D3, D5, D6, User D8, D10, D12, Reset ...

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... Stratix PCI Development Board Data Sheet Table 1 supports. Table 1. Stratix PCI Development Board Components & Interfaces (Part Type Component/ Interface FPGA Stratix device PCI PCI connector PCI level converters Memory DDR connector and DDR SDRAM Flash ® Configuration MAX configuration controller ...

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... Table 1. Stratix PCI Development Board Components & Interfaces (Part Type Component/ Interface User Indicator User LEDs Power Power connector Power +2.5-V power OK Indicators LED +1.5-V power OK LED +1.25-V power OK LED Test point +3.3 V +5.0 V +12.0 V -12.0 V Ground Altera Corporation Stratix PCI Development Board Data Sheet ...

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... Stratix PCI Development Board Data Sheet Table 1. Stratix PCI Development Board Components & Interfaces (Part Type Component/ Interface High-Speed HSDI port A, 8-bit Interface high-speed interface Connector (1) connector HSDI port B, 16-bit high-speed interface connector Agilent/Samtec ASP Probe Nios peripheral Expansion Prototype Card (PROTO1) ...

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... Functional This section describes the operation of the Stratix PCI development board. Figure 2 Description Figure 2. Stratix PCI Development Board Block Diagram PCI, PCI-X 256-MByte DDR SDRAM Memory HSDI Port A Connector (1) HSDI Port B Connectors (1) Agilent/Samtec ASP Differential Probe Connector (1) Expansion Prototype Card (PROTO1) ...

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... Note to (1) 8 Table 2 Board PCI High-Speed Development Kit, Stratix Professional Edition (Ordering code: PCI-BOARD/S60) PCI Development Kit, Stratix Edition (Ordering code: PCI-BOARD/S25) Table 3 for details. Application Width (Bits) 32 and 64 32 and 64 Table 3: PCI-X at 133 MHz is only available on the Starter Board. The Professional Board runs at a maximum of 100 MHz in PCI-X applications ...

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... U13 through U22 are IDT IDTQS3861Q level converters that convert between 5.0-V PCI backplane signals and Stratix 3.3-V signals. PCI Operating Mode The board settings dip switch bank (S1) sets the PCI operating mode and speed as shown in Table 4. PCI Operating Mode Selection Table 5 ...

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... Stratix PCI Development Board Data Sheet DDR SDRAM Memory The Stratix PCI development board was tested with the DDR SDRAM Memory Controller MegaCore function version 1.2.0. A 256-MByte DDR SDRAM memory module is installed in the 200-pin SODIMM connector (J10) and connects to banks 3 and 4 of the I/O Stratix device. ...

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... The MAX configuration controller configures the Stratix device when it is triggered by one of the following events: If the load is successful, the configuration done LED (D4) illuminates. Altera Corporation Stratix PCI Development Board Data Sheet Table 7. Due to the larger size of the configuration data for the Starter Board for details on the selection ...

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... Stratix device. See f Refer to the PCI High-Speed Development Kit, Stratix Professional Edition Getting Started User Guide for more details on the flash memory map for configuration images and general-purpose user data. Table 8. Configuration Image Selection ...

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... Clocks & Clock Distribution The Stratix PCI development board has multiple clock sources, with most of the clocks driven directly to the Stratix device. Using the fast and enhanced PLLs integrated within the Stratix device, the designer has significant flexibility to achieve the appropriate clock configuration for prototyping ...

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... Stratix PCI Development Board Data Sheet Table 9. Stratix Input Clocks Signal Name HSDI port B Connectors (J9.49, J8.112) Stratix device (U2.AB29) B1B_RX_CLKn HSDI port B Connectors (J9.47, J8.114) Stratix device (U2.AB28) B1B_RX_CLKp Stratix device (D18) DDR_CLK_FBIN On-Board 25-MHz 10/100 Ethernet CLK_25MHZ Oscillator (OSC1.4)) ...

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... B6_TX_CLKn B6_TX_CLKp Power c The Stratix PCI development board can be powered up from one of the following sources: The +2.5-, +1.5-, and +1.25-V power OK LEDs require the -12.0-V supply to illuminate. These LEDs only illuminate when the PCI connector J11 or power connector J18 supplies power to the board. ...

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... Stratix PCI Development Board Data Sheet Figure 3. 2.5-V Regulator +1.5-V Regulator Linear regulator U7 generates +1.5 V for the Stratix device from +3.3 V. +1.25-V Regulator Linear regulator U12 generates +1.25 V for DDR SDRAM memory termination and reference voltage. External Power Adaptor Receptacle J18 is a receptacle for power from a standard PC ATX power supply via the external power adapter cable ...

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... TP2 +12V TP7 -12V TP5 TP1 TP18 TP6 shows the power sourcing capability to the HSDI Stratix PCI Development Board Data Sheet 12. Description Description 3.3-V power. 5.0-V power. +12.0-V power. -12.0-V power. Ground, near the LCD connector. Ground, near the DDR SDRAM memory. ...

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... RX 18 shows the power sourcing capability to the Expansion shows the power indication LEDs. The power indication LEDs require the -12.0-V supply to illuminate. These LEDs only illuminate when the PCI connector J11 or power connector J18 supplies power to the board. Reference Designator D11 ...

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... Reserved. On Off Off Stratix configuration image selection. Select the flash memory block used to configure the Stratix device. See Off Table 8 on page Stratix PCI Development Board Data Sheet for instructions on using the LEDs. Color Description Red User defined. Red User defined. ...

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... Bank” on page 45 Table 19. User Dip Switch Bank User Dip Switch (S2) Positions 1 through 8 Expansion The Stratix PCI development board includes the following interfaces: Interfaces The HSDI port A and HSDI port B interfaces are only available on the Professional Board. 20 describes the pushbutton switches on the board. ...

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... HSDI Port A Interface 1 Bank 6 of the Stratix device contains an 8-bit HyperTransport-capable port wired to a connector that mates with several Broadcom reference boards. The connector at J13 allows the Stratix PCI development board to connect to other boards with a Broadcom-type HyperTransport connector. Compatible boards include: I/O Standard Jumper J20 allows HSDI port A to operate at 2 ...

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... It can be used at 2.5 V for HyperTransport or at 3.3 V for SPI-4.2, RapidIO, and other LVDS-based interfaces. J8 and J9 allow the Stratix PCI development board to connect to another board with a HyperTransport DUT connector. This interface operates 840 Mbits/second double data rate (DDR) with a 420 MHz clock. ...

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... HyperTransport DUT Chains The HyperTransport DUT specification defines 3 board types: The Stratix PCI development board operates as a host or cave board as determined by the application. Tunnel boards have at least two independent HyperTransport DUT interfaces and act as conduits between hosts, caves, and additional tunnels. ...

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... J8. The cave board is rotated 180° with respect to the host board. Figure 5. HyperTransport DUT Host/Cave Configuration Power Table tunnel or cave board when the Stratix PCI development board is used as a host board. 1 Table 22. HSDI Port B Host Board Power Sourcing Capability 24 ...

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... B link 0 receive signals with high-speed test equipment. Expansion Prototype Card (PROTO1) Interface J2 through J4 allow the Stratix PCI development board to accept optional boards with a Expansion Prototype Card (PROTO1) interface. Compatible boards include the Altera Nios Ethernet Development Kit (EDK) daughter card ...

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... DB-9 connector wired as an RS-232 serial DTE device. U10 shifts the RS-232 signals to LVTTL levels for connection to the Stratix device. LCD Display Interface J5 and J19 allow the Stratix PCI development board to accept an optional LCD display. Compatible displays include the Optrex T-51382D064J-FW-P-AA 6.4 display (not included with the kit). ...

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... Table 25. JTAG Chain Jumper Changing the JTAG Chain J17 is the JTAG chain bypass jumper. The JTAG chain changes when two Stratix PCI development boards are connected via the HSDI port B connector. Insert two shunts according to the configuration as shown in Table Table 26. JTAG Chain Bypass Jumper ...

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... Stratix signals to Apply power to the board. Configure the Stratix device. Installing the board into a universal PCI slot Attaching the board to an ATX power supply with the external power adaptor cable Attaching the board to an independently powered board via HSDI ...

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... Installing Standoffs for Bench-top Operation The Stratix PCI development board is initially configured for installation in a conventional PCI slot. Six standoffs and four screws are included to install on the board for bench-top operation Figure 7. Configuring the Board for Bench-top Operation Standoff location ...

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... Remove the screw adjacent to RN4. Turn the board face up, insert the screw through the same hole, and fasten a standoff to the screw. Gently place the board face down with the PCI bracket on the right Remove the lower screw/nut combination of the RS-232 connector (J7) ...

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... Configuration from the Flash Memory The Stratix device is volatile; therefore, it must be configured each time power is applied to the board. The Stratix PCI development board has a non-volatile configuration scheme that automatically configures the Stratix device with a factory default design, or, if selected, a user design, after power is applied ...

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... Refer to Quartus II Help for instructions on creating a HEX file. Write the contents of the HEX file into flash memory. See the PCI Development Kit, Stratix Edition Getting Started User Guide or PCI High-Speed Development Kit, Stratix Professional Edition Getting Started User Guide for instructions. ...

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... Table 27. PCI Signals (Part PCI_CLK PCI_RSTn PCI_LOCKn PCI_INTAn PCI_IDSEL PCI_REQn PCI_GNTn PCI_REQ64n PCI_ACK64n PCI_FRAMEn PCI_DEVSELn PCI_IRDYn PCI_TRDYn PCI_STOPn PCI_PAR PCI_PAR64 PCI_PERRn PCI_SERRn PCI_CBEn0 PCI_CBEn1 PCI_CBEn2 PCI_CBEn3 PCI_CBEn4 PCI_CBEn5 PCI_CBEn6 PCI_CBEn7 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 Altera Corporation ...

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... Stratix PCI Development Board Data Sheet Table 27. PCI Signals (Part PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_AD32 PCI_AD33 PCI_AD34 PCI_AD35 PCI_AD36 PCI_AD37 PCI_AD38 PCI_AD39 PCI_AD40 ...

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... Table 27. PCI Signals (Part PCI_AD47 PCI_AD48 PCI_AD49 PCI_AD50 PCI_AD51 PCI_AD52 PCI_AD53 PCI_AD54 PCI_AD55 PCI_AD56 PCI_AD57 PCI_AD58 PCI_AD59 PCI_AD60 PCI_AD61 PCI_AD62 PCI_AD63 System Configuration Table 28 Table 28. PCI System Configuration Signals Board Board Settings Dip Reference Switch Bank Positions (S1) PCIS Switch S1 Position 5 PSEL ...

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... Stratix PCI Development Board Data Sheet DDR SDRAM Memory The DDR SDRAM memory module installed at J10 uses SSTL-2 signaling and termination. A reference voltage of 1. supplied to banks 3 and 4 for SSTL-2 receiver biasing. On-board resistors provide fly-by termination at the DDR SDRAM memory connector pins. J10 is the SODIMM connector for the DDR SDRAM memory ...

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... DDR_DM4 DDR_DM5 DDR_DM6 DDR_DM7 DDR_DM8 DDR_DP0 DDR_DP1 DDR_DP2 DDR_DP3 DDR_DP4 DDR_DP5 DDR_DP6 DDR_DP7 DDR_DQ0 DDR_DQ1 DDR_DQ2 DDR_DQ3 Altera Corporation Stratix PCI Development Board Data Sheet DDR SDRAM Fly-By Terminator Connector (J10) 100 RN29.9 99 RN29.10 97 RN29.12 117 RN33.12 116 RN33.13 98 RN29.11 11 RN11.12 25 RN14 ...

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... Stratix PCI Development Board Data Sheet Table 29. DDR SDRAM Memory & Fly-By Terminators (Part DDR SDRAM Signal DDR_DQ4 DDR_DQ5 DDR_DQ6 DDR_DQ7 DDR_DQ8 DDR_DQ9 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15 DDR_DQ16 DDR_DQ17 DDR_DQ18 DDR_DQ19 DDR_DQ20 DDR_DQ21 DDR_DQ22 DDR_DQ23 DDR_DQ24 DDR_DQ25 DDR_DQ26 DDR_DQ27 ...

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... DDR_DQ57 DDR_DQ58 DDR_DQ59 DDR_DQ60 DDR_DQ61 DDR_DQ62 DDR_DQ63 Clocks Table 30 Table 30. DDR SDRAM Memory Clocks DDR_CLK0N DDR_CLK0P DDR_CLK1N Altera Corporation Stratix PCI Development Board Data Sheet DDR SDRAM Connector (J10) 141 145 151 153 142 146 152 154 163 165 171 175 ...

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... Stratix PCI Development Board Data Sheet Table 30. DDR SDRAM Memory Clocks DDR_CLK1P DDR_CLK2N DDR_CLK2P DDR_CLK_FBIN DDR_CLK_FBOUT Flash Memory Table 31 device and the MAX configuration controller. FLASH_RESETn FLASH_CEn FLASH_WEn FLASH_WPn FLASH_OEn FLASH_RDY_BSYn FLASH_BYTEn FLASH_A0 FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 ...

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... MAX Configuration Stratix Pin (U2) Controller (U1 141 Stratix PCI Development Board Data Sheet Stratix Pin (U2) Configuration Controller (U1) AM26 AJ22 AJ23 AL24 AH22 AM24 E14 F14 F15 C16 G19 J19 K19 J20 AB20 AF22 AD21 AG23 AC21 AD22 AB21 AA21 Table 32 Flash Memory (U3) ...

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... Stratix PCI Development Board Data Sheet Table 32. MAX Configuration Controller Connections (Part Configuration Signal EP1S_nCONFIG EP1S_nSTATUS FLASH_RESETn FLASH_CEn FLASH_WEn FLASH_OEn FLASH_RDY_BSYn FLASH_BYTEn FLASH_A0 FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14 FLASH_A15 FLASH_A16 FLASH_A17 FLASH_A18 ...

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... Board Settings Dip Switch Reference Bank Position USE M Switch S1 Position 8 MPGM1 Switch S1 Position 9 MPGM0 Switch S1 Position 10 shows the user connections between the MAX configuration User Signal MAX Configuration Controller (U1) Stratix PCI Development Board Data Sheet Flash Memory (U3) K19 42 J20 44 AB20 30 AF22 32 AD21 34 AG23 ...

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... Stratix PCI Development Board Data Sheet User LEDs Signals USER_LED0 through USER_LED7 are driven by the Stratix device through the MAX configuration controller to the user LEDs as shown in Figure 10 LED. Figure 10. User LED Drive & Control Signals Table 35. User LEDs Label Reference Stratix Device ...

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... Board Reference User Dip Switch Switch 2 Position 1 Switch 2 Position 2 Switch 2 Position 3 Switch 2 Position 4 Switch 2 Position 5 Switch 2 Position 6 Switch 2 Position 7 Switch 2 Position 8 Stratix PCI Development Board Data Sheet Destination Pin Signal USER_DIPSW0 USER_DIPSW1 USER_DIPSW2 USER_DIPSW3 USER_DIPSW4 USER_DIPSW5 USER_DIPSW6 USER_DIPSW7 ...

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... Stratix PCI Development Board Data Sheet Pushbutton Switches Table 38 switches. Table 38. Pushbuttons Board Reference SYS RESET USER RESET USER_PB1 USER_PB2 External Power Header Table 39 Table 39. External Power Header 3.3 V 5.0 V +12.0 V -12.0 V GND MAIN_SW HSDI Port A Interface HSDI port A is only available in the Professional Board. ...

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... Table 41. HSDI Port A Rx Interface (Part B6_RX_CLKn B6_RX_CLKp B6_RX_CTLn B6_RX_CTLp B6_RX_CADn0 B6_RX_CADp0 B6_RX_CADn1 B6_RX_CADp1 B6_RX_CADn2 B6_RX_CADp2 B6_RX_CADn3 B6_RX_CADp3 B6_RX_CADn4 B6_RX_CADp4 B6_RX_CADn5 B6_RX_CADp5 Altera Corporation Stratix PCI Development Board Data Sheet Signal Connector (J13) shows the HSDI port A Rx interface. Signal Connector (J13 ...

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... Stratix PCI Development Board Data Sheet Table 41. HSDI Port A Rx Interface (Part B6_RX_CADn6 B6_RX_CADp6 B6_RX_CADn7 B6_RX_CADp7 Table 42 Table 42. HSDI Port A Control Interface B6_RESETn B6_REF_CLK B6_PWROK B6_IO_RESETn B6_IO_CSn B6_IO_WRn B6_IO_OEn B6_IO_RDYn B6_IO_AD24 B6_IO_AD25 B6_IO_AD26 B6_IO_AD27 B6_IO_AD28 B6_IO_AD29 B6_IO_AD30 B6_IO_AD31 48 Signal Connector (J13) ...

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... B1A_TX_CADp6 B1A_TX_CADn7 B1A_TX_CADp7 Table 44 Table 44. HSDI Port B Link 0 Rx Interface (Part Signal QTE (Bottom) Connector (J9) B1A_RX_CLKn B1A_RX_CLKp B1A_RX_CTLn B1A_RX_CTLp Altera Corporation Stratix PCI Development Board Data Sheet Table 43 QSE (Top) Connector (J8) (J9) 115 117 83 85 139 141 133 135 127 129 ...

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... Stratix PCI Development Board Data Sheet Table 44. HSDI Port B Link 0 Rx Interface (Part Signal QTE (Bottom) Connector (J9) B1A_RX_CADn0 B1A_RX_CADp0 B1A_RX_CADn1 B1A_RX_CADp1 B1A_RX_CADn2 B1A_RX_CADp2 B1A_RX_CADn3 B1A_RX_CADp3 B1A_RX_CADn4 B1A_RX_CADp4 B1A_RX_CADn5 B1A_RX_CADp5 B1A_RX_CADn6 B1A_RX_CADp6 B1A_RX_CADn7 B1A_RX_CADp7 Table 45 Table 45. HSDI Port B Link 1 Tx Interface (Part ...

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... B1B_RX_CADn1 B1B_RX_CADp1 B1B_RX_CADn2 B1B_RX_CADp2 B1B_RX_CADn3 B1B_RX_CADp3 B1B_RX_CADn4 B1B_RX_CADp4 B1B_RX_CADn5 B1B_RX_CADp5 B1B_RX_CADn6 B1B_RX_CADp6 B1B_RX_CADn7 B1B_RX_CADp7 Altera Corporation Stratix PCI Development Board Data Sheet QSE (Top) Connector (J8) (J9) 108 100 102 shows the HSDI port B link 1 Rx connections. QSE (Top) Connector (J8) 49 112 ...

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... Stratix PCI Development Board Data Sheet Table 47 Table 47. HSDI Port B Control Interface Signal QTE (Bottom) Connector B1_SYS_RESETn B1_RESETn B1_REF_CLK_IN B1_REF_CLK_OUT B1_PWROK B1_REQn B1_STOPn B1_SMBCLK B1_SMBDAT Table 48 Table 48. HSDI Port B User Signals Signal QTE (Bottom) Connector B1_USER_A0 B1_USER_A1 B1_USER_B0 B1_USER_B1 B1_USER_C0 B1_USER_C1 ...

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... SCRUZ_IO1 SCRUZ_IO2 SCRUZ_IO3 SCRUZ_IO4 SCRUZ_IO5 SCRUZ_IO6 SCRUZ_IO7 SCRUZ_IO8 SCRUZ_IO9 SCRUZ_IO10 SCRUZ_IO11 SCRUZ_IO12 SCRUZ_IO13 SCRUZ_IO14 SCRUZ_IO15 SCRUZ_IO16 Altera Corporation Stratix PCI Development Board Data Sheet QSE (Top) Connector (J8) (J9) 7 154 shows the Expansion Prototype Card (PROTO1) interface. Signal Connector J3.1 J4.11 J4.9 J4 ...

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... Stratix PCI Development Board Data Sheet Table 50. Expansion Prototype Card (PROTO1) Connectors (Part SCRUZ_IO17 SCRUZ_IO18 SCRUZ_IO19 SCRUZ_IO20 SCRUZ_IO21 SCRUZ_IO22 SCRUZ_IO23 SCRUZ_IO24 SCRUZ_IO25 SCRUZ_IO26 SCRUZ_IO27 SCRUZ_IO28 SCRUZ_IO29 SCRUZ_IO30 SCRUZ_IO31 SCRUZ_IO32 SCRUZ_IO33 SCRUZ_IO34 SCRUZ_IO35 SCRUZ_IO36 SCRUZ_IO37 SCRUZ_IO38 SCRUZ_IO39 Note to (1) RS-232 Table 51 Table 51. RS-232 Serial Interface ...

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... MICTOR_DE4 MICTOR_DE5 MICTOR_DE6 MICTOR_DE7 MICTOR_DE8 MICTOR_DE9 MICTOR_DE10 MICTOR_DE11 MICTOR_DE12 MICTOR_DE13 MICTOR_DE14 MICTOR_DE15 MICTOR_DO0 MICTOR_DO1 MICTOR_DO2 MICTOR_DO3 MICTOR_DO4 MICTOR_DO5 MICTOR_DO6 Altera Corporation Stratix PCI Development Board Data Sheet Level Shifter A Level Shifter B U10.7 U10.10 shows the LCD header connections. Signal Connector Pin (J5 ...

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... Stratix PCI Development Board Data Sheet JTAG Table 53 Table 53. JTAG JTAG_TCK JTAG_CONN_TDO JTAG_CONN_TDI JTAG_TMS GND 3.3V Agilent/Samtec ASP Differential Probe Table 54 to the Agilent/Samtec ASP differential probe. Table 54. Agilent/Samtec ASP Differential Probe (Part Probe Signal ASP Pin (J12) SAMTEC_RX_CLKn SAMTEC_RX_CLKp SAMTEC_RX_CTLn ...

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... MICTOR_DO6 MICTOR_DO7 Altera Corporation Termination Isolation Resistor Resistor 35 R91.1 R71.1 36 R92.1 R72.1 shows the connections to the Mictor header. Signal Mictor Header Pin (J6) Stratix PCI Development Board Data Sheet Stratix Pin Signal (U2) W31 B1A_RX_CADn7 W32 B1A_RX_CADp7 Stratix Pin (U2) 6 G29 5 F32 37 G30 35 ...

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... MICTOR_DO12 MICTOR_DO13 MICTOR_DO14 MICTOR_DO15 Schematics The subsequent pages provide the schematics for the Stratix PCI development board. Copyright specific device designations, and all other words and logos that are identified as trademarks and/or service 101 Innovation Drive marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries ...

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... CONF_DONEn LED signal from CONF_DONE config signal, Changed C1/C2 to 47uF. PAGE 1 Title, Notes, Revision History 2 Primary PCI 3 PCI Voltage Limit Switches 4 PCI Voltage Switch Bypass Resistors 5 Stratix Bank 7, 8, LEDs BANK 2 VCCIO = 3.3V 6 DDR SDRAM SO-DIMM MICTOR, LCD HEADER 7 DDR-SDRAM Terminations ...

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... Notes: (1) Pin B38 = GND in PCI 2.2 and PCI-XCAP in PCI-X. It can be grounded or 10K pullup here. (2) Pin A14 = 3.3Vauxin PCI2.2 but is unused for our board and PCI core. (3) Pins B9 & B11 are power requirement strapping pins. We are strapped for maximum 25W power. ...

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... B2 LPCI_AD5 PCI_AD5 LPCI_AD7 PCI_AD7 LPCI_AD8 PCI_AD8 LPCI_AD10 PCI_AD10 GND QS3861_SO_2 A Copyright (c) 2003, Altera Corporation. All Rights Reserved PCI Voltage Limit Switches R56 4.7K TOP #4 U15 4.3V_VCC VCC LPCI_AD49 PCI_AD49 LPCI_AD51 PCI_AD51 LPCI_AD53 PCI_AD53 LPCI_AD55 PCI_AD55 LPCI_AD57 PCI_AD57 LPCI_AD59 PCI_AD59 LPCI_AD61 PCI_AD61 ...

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... LPCI_AD3 PCI_AD3 3 14 LPCI_AD5 PCI_AD5 4 13 LPCI_AD7 PCI_AD7 5 12 LPCI_AD8 PCI_AD8 6 11 LPCI_AD10 PCI_AD10 Copyright (c) 2003, Altera Corporation. All Rights Reserved PCI Voltage Switch Bypass Resistors TOP #4 RN36 LPCI_AD49 PCI_AD49 4 13 LPCI_AD51 PCI_AD51 5 12 LPCI_AD53 PCI_AD53 6 11 LPCI_AD55 PCI_AD55 LPCI_INTAn 3 LPCI_AD57 ...

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... BANK 7 (3.3V PCI & 3.3V LVTTL) U2G LPCI_AD31 AK4 DQ0B0 LPCI_REQn 3,4 AK3 DQ0B1 LPCI_AD26 AH5 E DQ0B2 LPCI_AD27 AJ5 DQ0B3 LPCI_AD30 AJ4 DQ0B4 LPCI_INTAn 3,4 AM4 DQ0B5 CPLD_USER0 AL4 DQ0B6 LPCI_GNTn 3,4 AL3 DQ0B7 LPCI_AD28 AK5 DQS0B LPCI_CBEn3 3,4 AJ6 ...

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... LP2995M + C228 + C229 100uF 100uF 10V 10V Tantalum Tantalum SSTL2 TERMINATION VOLTAGE REGULATOR (1.5A / 3.0A Peak) Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Stratix PCI Development Board Size Document Number B Date: Wednesday, February 12, 2003 7,9 DDR_DQ[63..0] 7,9 DDR_BA[2..0] E 7,9 DDR_A[13 ...

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... NOTE: ALL OF THE 56 OHM PULL UP RESISTORS MUST BE PLACED AFTER THE SODIMM (i.e. AFTER THE CONNECTOR) AND AS CLOSE AS POSSIBLE TO THE SODIMM. Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Stratix PCI Development Board Size Document Number B Date: Wednesday, February 12, 2003 4 3 ...

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... Two user-defined 5,17 USER_PB[2..1] pushbuttons for any 5,14,17 SYS_RESETn use. 5,17 USER_RESETn 5,17 CPLD_USER[1..0] USER_PB2 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Stratix PCI Development Board Size Document Number B Date: Wednesday, February 12, 2003 SCRUZ_IO[39..0] 13 LAN_D[31..0] 13 LAN_A[14..0] 13 LAN_BEn[3 ...

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... DQ0T7 GPIO_B4_38 DDR_DQS0 C5 DQS0T EP1S40F1020 On-chip termination biasing resistors 2.5V RUP4 R35 250 RD N4 R36 250 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Stratix PCI Development Board Size Document Number B Date: Wednesday, February 12, 2003 6,7 DDR_DQ[63..0] 6,7 DDR_DP[7..0] 6,7 DDR_A[13 ...

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... B1_USER_A0 152 PIN_152 JTAG_SAMTEC_TDO 154 PIN_154 156 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 PIN_156 158 PIN_158 Title 160 PIN_160 Stratix PCI Development Board 3.3V 175 GND15 Internal Ground Plane Pins 176 GND16 Size Document Number B Date: Wednesday, February 12, 2003 4 3 ...

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... GND41 Bank 6 Transmit (Outputs from this board) 129 130 GND42 GND43 131 132 GND44 GND45 QTE-060-EM Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Stratix PCI Development Board Size Document Number B Date: Wednesday, February 12, 2003 BANK 1A HDSI DEBUG 10,12 B1A_RX_CADp[7..0] 10,12 B1A_RX_CADn[7 ...

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... R135 B6_RX_CADp2 R136 B6_RX_CADp3 R137 B6_RX_CADp4 R138 B6_RX_CADp5 R139 B6_RX_CADp6 R140 B6_RX_CADp7 R141 B6_RX_CTLp Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Stratix PCI Development Board Size Document Number B Date: Wednesday, February 12, 2003 HSDI BANK 1A TX INTERFACE 10 B1A_TX_CLKp 10 B1A_TX_CLKn 10 B1A_TX_CTLp ...

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... RN8 10K Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121 Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121 Title Stratix PCI Development Board Size Document Number B Date: Wednesday, February 12, 2003 3.3V L10 1 2 47nH C225 C226 0.001uF 1.0uF X7R X7R C 8 LAN_D[31..0] 8 LAN_A[14..0] 8 LAN_BEn[3 ...

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... MICTOR_DO4 MICTOR_DO5 MICTOR_DE13 MICTOR_DE15 MICTOR_DE14 31 31 DF9B-31P-1V Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Stratix PCI Development Board Size Document Number B 150-0216200-01 Date: Wednesday, February 12, 2003 SANTA CRUZ 8 SCRUZ_IO[39..0] MICTOR / LCD 8 MICTOR_DE[15.. MICTOR_DO[15..0] 8 MICTOR_CLKO 8 MICTOR_CLKE D C MICTOR_CLKE => LCD_CLK MICTOR_DE0 => ...

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... PLL_ENA 16 AF19 PLL_ENA C17 PLL5_FBn D17 PLL5_FBp AM17 PLL6_FBn AL17 PLL6_FBp EP1S40F1020 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Stratix PCI Development Board Size Document Number B Date: Wednesday, February 12, 2003 PLL5 Output Vcc = 2.5V PLL6 Output Vcc = 3.3V 6 DDR_CLK0n ...

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... ALERTn 2 15 SMB_CLK 3. SMB_DATA 4 13 PLL_ENA AUX_IN 2.5V_SHDNn 8 9 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Stratix PCI Development Board Size Document Number B Date: Wednesday, February 12, 2003 U2L P20 VCCIO1_1 GND39 R14 VCCIO1_2 GND40 E R16 VCCIO1_3 GND41 R17 VCCIO1_4 ...

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... HEADER ByteBlaster / MasterBlaster Header (uses JTAG mode only) Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Stratix PCI Development Board Size Document Number B Date: Wednesday, February 12, 2003 FLASH_D[15..0] 5 FLASH_A[21..0] 5 USER_LED[7..0] 2 PCI_XCAP 2 PCI_M66EN E 5 USER_LED_DRV[7..0] 5 FLASH_OEn 5 FLASH_CEn ...

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... TAN D Bulk Decoupling 1.5V 2.5V 3.3V C38 C39 C40 + 100uF + 100uF + 100uF 10V 10V 10V Tantalum Tantalum Tantalum Place near PCI Connector +12V -12V C C100 C101 0.1uF 0.1uF X7R X7R B C129 C130 C131 0.1uF 0.1uF 0.1uF X7R X7R X7R C143 C144 C145 0 ...