PEF82902FV11XP Lantiq, PEF82902FV11XP Datasheet - Page 65

• Manufacturer Part Number: PEF82902FV11XP
• Manufacturer: Lantiq

Specifications of PEF82902FV11XP

• Lead Free Status / Rohs Status: Supplier Unconfirmed

•
Figure 28
When the TIC bus is seized by the T-SMINT
occupied via the DU Ch2 Bus Accessed-bit state ’0’ until the access request is
withdrawn. After a successful bus access, the T-SMINT
lower priority class, that is, a new bus access cannot be performed until the status "bus
free" is indicated in two successive frames.
If none of the devices connected to the IOM
I0 channels, the TIC bus address 7 will be present. The device with this address will
therefore have access, by default, to the D and C/I0 channels.
Note: Bit BAC (CIX0 register) should be reset by the
2.3.5.3
The availability of the DU D channel is indicated in bit 5 "Stop/Go" (S/G) of the last octet
in DD channel 2
MODEH.DIM2-0=0x1.
S/G = 1 : stop
S/G = 0 : go
The Stop/Go bit is available to other layer-2 devices connected to the IOM
to determine if they can access the D channel in upstream direction.
Data Sheet
requested, to grant other devices access to the D and C/I0 channels.
DU
Stop/Go Bit Handling
Structure of Last Octet of Ch2 on DU
B1
(Figure
B2
MON0
29). The arbitration mechanism must be activated by setting
D CI0
MR
MX
IC1
53
â
IC2
â
-2 interface request access to the D and C/
I, the bus is identified to other devices as
BAC
MON1
TIC-BUS Address (TAD 2 - 0)
Bus Accessed ("1" no TIC-BUS Access)
2
CI1
TAD
1
â
0
C when access is no more
I is automatically set into a
MR
MX
Functional Description
TAD
BAC
â
PEF 82902
-2 interface
ITD02575.vsd
2001-11-09