PEF82902FV11XP Lantiq, PEF82902FV11XP Datasheet - Page 143

• Manufacturer Part Number: PEF82902FV11XP
• Manufacturer: Lantiq

Specifications of PEF82902FV11XP

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Important: This register - except bit DPRIO - is writable only if the Layer 1 state machine
of the device is disabled (S_CONF0.L1SW = 1) and implemented in software! With the
device layer 1 state machine enabled, the signals from this register are automatically
generated. DPRIO can also be written in intelligent NT mode.
XINF
DPRIO
PD
LP_A
4.5.5
SQRR
Value after reset: 00
Data Sheet
SQRR - S/Q-Channel Receive Register
Transmit INFO
000 =
001 =
010 =
011 =
100 =
101 =
11x =
D-Channel Priority
0 =
1 =
Power Down
0 =
1 =
Loop Analog
The setting of this bit corresponds to the C/I command ARL.
0 =
1 =
Transmit INFO 0
reserved
Transmit INFO 2
Send continuous pulses at 192 kbit/s alternating or 96 kHz
rectangular, respectively (TM2)
Send single pulses at 4 kbit/s with alternating polarity
corresponding to 2 kHz fundamental mode (TM1)
reserved
Priority class 1 for D channel access on IOM
Priority class 2 for D channel access on IOM
The transceiver is set to operational mode
The transceiver is set to power down mode
Analog loop is open
Analog loop is closed internally or externally according to the EXLP
bit in the S_CONF0 register
H
Transmit INFO 4
read
131
Register Description
Address:
PEF 82902
2001-11-09
35
H