PEF82902FV11XP Lantiq, PEF82902FV11XP Datasheet - Page 154

• Manufacturer Part Number: PEF82902FV11XP
• Manufacturer: Lantiq

Specifications of PEF82902FV11XP

• Lead Free Status / Rohs Status: Supplier Unconfirmed

DPS
TSS
4.7.3
CDAx_CR
Register
CDA1_CR
CDA2_CR
EN_TBM Enable TIC Bus Monitoring
EN_I1,
EN_I0
Data Sheet
Note: For the CDA (controller data access) data the input is determined by the
CDAx_CR.SWAP bit. If SWAP = ‘0’ the input for the CDAxy data is vice versa to
the output setting for CDAxy. If the SWAP = ‘1’ the input from CDAx0 is vice
versa to the output setting of CDAx1 and the input from CDAx1 is vice versa to
the output setting of CDAx0.
7
0
CDAx_CR - Control Register Controller Data Access CH1x
Data Port Selection
0 =
1 =
Timeslot Selection
Selects one of the 12 timeslots from 0...11 on the IOM
data channels.
0 =
1 =
Enable Input CDAx1, CDAx0
0
The data channel xy of the functional unit XXX is output on DD.
The data channel xy of the functional unit XXX is input from DU.
The data channel xy of the functional unit XXX is output on DU.
The data channel xy of the functional unit XXX is input from DD.
The TIC bus monitoring is disabled
The TIC bus monitoring with the CDAx0 register is enabled. The
TSDPx0 register must be set to 08
for monitoring from DD.
Value after Reset
00
00
H
H
EN_TBM
EN_I1
read/write
142
EN_I0
Register Address
4E
4F
H
H
H
for monitoring from DU, or 88
EN_O1
Register Description
®
-2 interface for the
EN_O0
Address: 4E-4F
PEF 82902
2001-11-09
SWAP
0
H
H