PEB20570FV31XP Infineon Technologies, PEB20570FV31XP Datasheet - Page 282
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PEB20570FV31XP
Manufacturer Part Number
PEB20570FV31XP
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEB20570FV31XP.pdf
(308 pages)
Specifications of PEB20570FV31XP
Lead Free Status / Rohs Status
Compliant
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Table 76
Parameter
FSC Clock Period High in a
short-pulse FSC cycle
1)
2)
3)
Figure 75
Data Sheet
Short-Pulse
FSC rises and falls by DCL rising edge, and should be sampled with the falling edge of DCL, in the other chips,
connected to the IOM-2 interface of the DELIC.
In a long-pulse FSC cycle, FSC is generated with a 50% duty cycle. FSC Clock Period Low is the complement
of this parameter to 125 s.
In a short-pulse FSC cycle, FSC is high for exactly one cycle of DCL, thus it is dependent on the frequency of
DCL. FSC Clock Period Low is the complement of this parameter to 125 s.
Long-Pulse
DCL
FSC
FSC
t
FDE
FSC (IOM-2 and IOM-2000 Frame-Sync) Timing (cont’d)
FSC Timing IOM-2
t
FDE
t
3)
HSC
t
Symbo
l
t
FDE
HSC
t
HLC
Electrical Characteristics and Timing Diagrams
min.
2.5
1.2
640
480
235
t
FDE
Limit Values
265
t
FSC
typ.
2.604 2.7
1.302 1.4
651
488
244
t
FSC
max.
660
490
255
Unit Notes
ns
ns
ns
s
s
DCL = 384 kHz
DCL = 768 kHz
DCL = 1536 kHz
DCL = 2048 kHz
DCL = 4096 kHz
PEB 20570
PEB 20571
2003-07-31
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