PEB20570FV31XP Infineon Technologies, PEB20570FV31XP Datasheet - Page 107

• Manufacturer Part Number: PEB20570FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20570FV31XP

• Lead Free Status / Rohs Status: Compliant

Figure 31
4.2.10
4.2.10.1 Framing Bit (F-Bit)
The framing (F) bit is recognized on the TRANSIU interface, when both data and control
bits are equal to ‘1’. In the transmit direction the data and control bits are inserted by the
TRANSIU at the beginning of every transmitted frame; in the receive direction the
framing bit is used for frame start recognition.
4.2.10.2 Multiframing Bits
In S/T interface, the multiframe includes 20 S/T frames. The start of a multiframe is
indicated by the M- and F
to ‘1’ in every 5
The S/Q channel provides the additional capability for data exchange between LT-S and
TE or between the Central Office (CO) and the LT-T at the multiframe level. In the LT-S-
to-TE direction the S-channel (S-bit in S/T frame) is used. In the opposite direction (TE
to LT-S) the data is transferred on the Q-channel. The Q-bits are defined to be the bits
in the F
TE to LT-S direction. A multiframe is provided for structuring the Q-bits in groups of four
(Q1-Q4).
The Q- and S-channel coding with respect to the frame number is shown in
Data Sheet
a
bit position of every 5
S/T Mode Control and Framing Bits on IOM-2000
Collision Detection in the LT-T Mode
th
frame).
DELIC
a
-bits (the M-bit is set to ‘1’ in every 20
th
E
E / D
logic
frame. The Q-bit position is identified by F
D
Collision
Status
90
HDLCU
TRANSIU
Data
buffer
DSP
Functional Description
th
frame, the F
PEB 20570
PEB 20571
a
Table
= ‘1’ in the
2003-07-31
a
-bit is set
29.