PEB20570FV31XP Infineon Technologies, PEB20570FV31XP Datasheet - Page 162

• Manufacturer Part Number: PEB20570FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20570FV31XP

• Lead Free Status / Rohs Status: Compliant

4.11.6
The IOM-2000 interface uses the same FSC like IOM-2, whereas the data clock
DCL2000 is a dedicated pin (always output).
4.11.7
REFCLK is an I/O pin for synchronizing the PCM interface (to 8 kHz or 512 kHz).
The clock master DELIC may synchronize the internal clocks to REFCLK by selecting
REFCLK as the reference clock source.
A clock slave DELIC may use REFCLK as output, when REFCLK is driven by the XCLK
input pin. The slave DELIC may transfer the XCLK signal to the clock master DELIC, and
enable the clock master to synchronize to a layer-1 device, which is connected to
another DELIC in the system.
4.11.8
Any of the next signals may be provided to the GHDLC channel as input clock:
1. LCLK Input Pin
2. 2.048 MHz, 4.096 MHz, 8.192 MHz or 16.384 MHz
Note: One of these signals must be selected as the clock of the GHDLC channel when
Note: It’s not possible to operate a GHDLC-channel with 16.384 MHz. However if the
Data Sheet
This option is possible only when a LNC interface is assigned to the GHDLC unit.
These clock signals are generated internally by the PCM clocking path. The selected
internal clock is also driven outward via LCLK.
the DELIC is the clock master of this channel.
respective port isn’t used this clock can be driven externally.
IOM-2000 Clock Selection
REFCLK Configuration
GHDLC Clock Selection
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Functional Description
PEB 20570
PEB 20571
2003-07-31