ADMCF328BRZ Analog Devices Inc, ADMCF328BRZ Datasheet - Page 23

• Manufacturer Part Number: ADMCF328BRZ
• Manufacturer: Analog Devices Inc

Specifications of ADMCF328BRZ

• Operating Current: 123mA
• Operating Temperature Classification: Industrial
• Package Type: SOIC W
• Operating Supply Voltage (min): -0.3V
• Operating Supply Voltage (max): 7V
• Lead Free Status / Rohs Status: Compliant

SYSTEM CONTROLLER
The system controller block of the ADMCF328 performs the
following functions:
10. Performs a reset of the motor control peripherals and control
SPORT1 Control
Both data receive pins are multiplexed internally into the single
data receive input of SPORT1 as shown in Figure 20. Two con-
trol bits in the MODECTRL register control the state of the
SPORT1 pins by manipulating internal multiplexers in the
ADMCF328.
REV. A
1. Manages the interface and data transfer between the DSP core
2. Handles interrupts generated by the motor control peripherals
3. Controls the ADC multiplexer select lines.
4. Enables PWMTRIP and PWMSYNC interrupts.
5. Controls the multiplexing of the SPORT1 pins to select
6. Controls the PWM single/double update mode.
7. Controls the ADC conversion time modes.
8. Controls the auxiliary PWM operation mode.
9. Contains a status register (SYSSTAT) that indicates the state
and the motor control peripherals.
and generates a DSP core interrupt signal IRQ2.
either DR1A or DR1B data receive pins. It also allows con-
figuration of SPORT1 as a UART interface.
of the PWMTRIP pin, the watchdog timer, and the PWM
timer.
registers following a hardware, software, or watchdog initi-
ated reset.
–23–
Bit 4 of the MODECTRL register (DR1SEL) selects between the
two data receive pins. Setting Bit 4 of MODECTRL connects pin
DR1B to the internal data receive port DR1 of SPORT1. Clearing
Bit 4 connects DR1A to DR1.
Setting Bit 5 of the MODECTRL register (SPORT1 Mode) con-
figures the serial port for UART mode. In this mode, the DR1 and
RFS1 pins of the internal serial port are connected together. Addi-
tionally, setting the SPORT1 Mode bit connects the FL1 flag of
the DSP to the external PIO5/RFS1 pin.
Flag Pins
The ADMCF328 provides flag pins. The alternate configuration
of SPORT1 includes a Flag In (FI) and Flag Out (FO) pin.
This alternate configuration of SPORT1 is selected by Bit 10 of
the DSP system control register, SYSCNTL at data memory
address, 0x3FFF. In the alternate configuration, the DR1 pin
(either DR1A or DR1B depending upon the state of the DR1SEL
bit) becomes the FI pin and the DT1 pin becomes the FO pin.
Additionally, RFS1 is configured as the IRQ0 interrupt input
and TFS1 is configured as the IRQ1 interrupt. The serial port
clock, SCLK1, is still available in the alternate configuration.
Development Tools
Users are recommended to obtain the ADMCF328-EVALKIT
from Analog Devices. The tool kit contains everything required
to quickly and easily evaluate and develop applications using the
ADMCF328 and ADMC328 DSP Motor Controllers. Please
contact your ADI sales representative for ordering information.
DSP
CORE
SPORT1
Figure 20. Internal Multiplexing of SPORT1 Pins
SCLK1
RFS1
TFS1
DR1
DT1
FL1
MODECTRL (5 . . . 4)
ADMCF328
UARTEN
ADMCF328
DR1SEL
PIO1/DT1
PIO2/DR1B
PIO0/TFS1
PIO4/DR1A
PIO5/RFS1
PIO3/SCLK1