ADMCF328BRZ Analog Devices Inc, ADMCF328BRZ Datasheet - Page 14

• Manufacturer Part Number: ADMCF328BRZ
• Manufacturer: Analog Devices Inc

Specifications of ADMCF328BRZ

• Operating Current: 123mA
• Operating Temperature Classification: Industrial
• Package Type: SOIC W
• Operating Supply Voltage (min): -0.3V
• Operating Supply Voltage (max): 7V
• Lead Free Status / Rohs Status: Compliant

ADMCF328
Each switching edge is moved by an equal amount (PWMDT
× t
pulse, whose width is set by the PWMSYNCWT register, is also
shown. Bit 3 of the SYSSTAT register indicates which half cycle
is active. This can be useful in double update mode, as will be
discussed later.
The resultant on-times of the PWM signals shown in Figure 7
may be written as:
The corresponding duty cycles are:
Obviously, negative values of T
because the minimum permissible value is zero, corresponding
to a 0% duty cycle. In a similar fashion, the maximum value is
T
The output signals from the timing unit for operation in double
update mode are shown in Figure 8. This illustrates a completely
general case where the switching frequency, dead time and duty
cycle are all changed in the second half of the PWM period. Of
course, the same value for any or all of these quantities could be
used in both halves of the PWM cycle. However, it can be seen
that there is no guarantee that symmetrical PWM signals will be
produced by the timing unit in this double update mode. Addi-
tionally, it is seen that the dead time is inserted into the PWM
signals in the same way as in the single update mode.
SYSSTAT (3)
SYSSTAT (3)
S
Figure 7. Typical PWM Outputs of Three-Phase Timing
Unit in Single Update Mode
Figure 8. Typical PWM Outputs of Three-Phase Timing
Unit in Double Update Mode
PWMSYNC
CK
PWMSYNC
, corresponding to a 100% duty cycle.
T
T
) to preserve the symmetrical output patterns. The PWMSYNC
AH
AL
d
d
AH
AL
AH
AL
AH
AL
=
=
2
=
2
=
2
×
2
T
×
T
T
T
AL
(
AH
(
S
PWMDT
S
PWMSYNCWT
PWMTM
PWMDT
PWMCHA
=
PWMTM
=
PWMTM
PWMTM
PWMCHA
1
1
PWMCHA
1
–
+ 1
PWMCHA
PWMTM
–
PWMCHA
PWMDT
–
1
AH
–
PWMCHA
PWMTM
PWMCHA
and T
PWMDT
PWMCHA
)
–
AL
2
×
PWMTM
PWMDT
PWMSYNCWT
t
are not permitted
PWMSYNCWT + 1
CK
PWMTM
–
PWMDT
2
2
2
PWMDT
PWMDT
)
2
×
+ 1
t
CK
2
–14–
In general, the on-times of the PWM signals in double update
mode are defined by:
where the subscript 1 refers to the value of that register during
the first half cycle and the subscript 2 refers to the value during
the second half cycle. The corresponding duty cycles are:
because for the completely general case in double update mode,
the switching period is given by:
Again, the values of T
zero and T
PWM signals similar to those illustrated in Figure 7 and Figure
8 can be produced on the BH, BL, CH, and CL outputs by pro-
gramming the PWMCHB and PWMCHC registers in a manner
identical to that described for PWMCHA.
The PWM controller does not produce any PWM outputs until
all of the PWMTM, PWMCHA, PWMCHB, and PWMCHC
registers have been written to at least once. After these registers
have been written, the counters in the three-phase timing unit
are enabled. Writing to these registers also starts the main PWM
timer. If during initialization, the PWMTM register is written
before the PWMCHA, PWMCHB, and PWMCHC registers,
the first PWMSYNC pulse (and interrupt if enabled) will be gener-
ated (1.5 × t
PWMTM register in single update mode. In double update mode,
the first PWMSYNC pulse will be generated (t
seconds after the initial write to the PWMTM register in single
update mode.
Effective PWM Resolution
In single update mode, the same values of PWMCHA, PWMCHB
and PWMCHC are used to define the on-times in both half
cycles of the PWM period. As a result, the effective resolution of
the PWM generation process is 2 t
CLKOUT) since incrementing one of the duty cycle registers by
T
AH
T
AL
=
(
=
d
d
PWMCHA
AH
AL



S
PWMTM
.
PWMCHA
T
CK
=
=
=
−
=
–
S
T
PWMTM
(
T
PWMCHA
(
T
PWMDT
PWMCHA
× PWMTM) seconds after the initial write to the
T
PWMTM
=
PWMTM
AL
AH
S
S
(
1
PWMTM
+
1
AH
PWMCHA
PWMTM
+
2
PWMTM
and T
1
1
PWMTM
−
1
1
1
+
+
2
PWMDT
+
+
+
PWMDT
PWMTM
+
1
PWMTM
PWMCHA
PWMTM
AL
PWMDT
+
2
1
PWMTM
1
are constrained to lie between
−
+
CK
+
2
PWMDT
PWMTM
1
PWMTM
−
(or 100 ns for a 20 MHz
2
−
2
PWMCHA
2
1
2
PWMDT
2
+
+
PWMCHA
2
PWMDT
1
)
−
×
2
CK
2
PWMDT
t
CK
× PWMTM)
2
1
−
2

 ×

)
1
)
REV. A
2
t
)
CK
×
t
CK