ADMCF328BRZ Analog Devices Inc, ADMCF328BRZ Datasheet - Page 16

• Manufacturer Part Number: ADMCF328BRZ
• Manufacturer: Analog Devices Inc

Specifications of ADMCF328BRZ

• Operating Current: 123mA
• Operating Temperature Classification: Industrial
• Package Type: SOIC W
• Operating Supply Voltage (min): -0.3V
• Operating Supply Voltage (max): 7V
• Lead Free Status / Rohs Status: Compliant

ADMCF328
Figure 9. An example of PWM signals suitable for ECM
control. PWMCHA = PWMCHB, BH/BL are a crossover pair.
AL, BH, CH, and CL outputs are disabled. Operation is in
single update mode.
Gate Drive Unit: PWMGATE Register
The gate drive unit of the PWM controller adds features that
simplify the design of isolated gate drive circuits for PWM
inverters. If a transformer-coupled power device gate drive ampli-
fier is used, the active PWM signal must be chopped at a high
frequency. The PWMGATE register allows the programming of
this high frequency chopping mode. The chopped active PWM
signals may be required for the high-side drivers only, for the
low-side drivers only, or for both the high-side and low-side
switches. Therefore, independent control of this mode for both
high- and low-side switches is included with two separate control
bits in the PWMGATE register.
Typical PWM output signals with high-frequency chopping
enabled on both high-side and low-side signals are shown in
Figure 10. Chopping of the high-side PWM outputs (AH, BH,
and CH) is enabled by setting Bit 8 of the PWMGATE register.
Chopping of the low-side PWM outputs (AL, BL, and CL) is
enabled by setting Bit 9 of the PWMGATE register. The high
chopping frequency is controlled by the 8-bit word (GDCLK)
written to Bits 0 to 7 of the PWMGATE register. The period
and the frequency of this high frequency carrier are:
The GDCLK value may range from 0 to 255, corresponding
to a programmable chopping frequency rate from 19.5 kHz to
5 MHz for a 20 MHz CLKOUT rate. The gate drive features
must be programmed before operation of the PWM controller
and typically are not changed during normal operation of the
PWM controller. Following a reset, by default, all bits of the
PWMGATE register are cleared so that high frequency chopping
is disabled.
AH
BH
CH
AL
BL
CL
2
PWMDT
T
CHOP
PWMTM
f
CHOP
=
= PWMCHB
PWMCHA
[
4
=
×
[
4
(
GDCLK
×
(
GDCLK
= PWMCHB
f
PWMCHA
CLKOUT
+
PWMTM
1
+
)
]
1
×
)
]
t
2
CK
PWMDT
–16–
Figure 10. Typical PWM signals with high frequency gate
chopping enabled on both high-side and low-side switches
(GDCLK is the integer equivalent of the value in Bits 0 to 7
of the PWMGATE register.)
PWM Shutdown
In the event of external fault conditions, it is essential that the
PWM system be instantaneously shut down. Two methods of
sensing a fault condition are provided by the ADMCF328. For
the first method, a low level on the PWMTRIP pin initiates
an instantaneous, asynchronous (independent of DSP clock)
shutdown of the PWM controller. This places all six PWM
outputs in the OFF state, disables the PWMSYNC pulse and
associated interrupt signal, and generates a PWMTRIP interrupt
signal. The PWMTRIP pin has an internal pull-down resistor so
that even if the pin becomes disconnected, the PWM outputs will
be disabled. The state of the PWMTRIP pin can be read from
bit 0 of the SYSSTAT register.
The second method for detecting a fault condition is through the
I
pin monitors the feedback signals from a dc bus current sensing
resistor that represents the total current in the motor. When the
voltage of I
will be internally pulled low. The negative edge of the internal
PWMTRIP will generate a shutdown in the same manner as a
negative edge on pin PWMTRIP.
It is possible through software to initiate a PWM shutdown by
writing to the 1-bit read/write PWMSWT register (0x2061).
Writing to this bit generates a PWM shutdown in a manner
identical to the PWMTRIP or I
shutdown, it is possible to determine if the shutdown was gener-
ated from hardware or software by reading the same PWMSWT
register. Reading this register also clears it.
Restarting the PWM after a fault condition is detected requires
clearing the fault and reinitializing the PWM. Clearing the fault
requires that PWMTRIP returns to a HI state and I
to a voltage greater than the I
fault has been cleared, the PWM can be restarted by writing to
registers PWMTM, PWMCHA, PWMCHB, and PWMCHC. After
the fault is cleared and the PWM registers are initialized, internal
timing of the three-phase timing unit will resume, and the
new duty cycle values will be latched on the next rising edge
of PWMSYNC.
SENSE
pin in the analog block of the ADMCF328. The I
2
PWMDT
SENSE
[4
PWMTM
(GDCLK+1)
goes below I
PWMCHA
t
CK
]
SENSE
SENSE
SENSE
PWMCHA
trip threshold, PWMTRIP
trip threshold. After the
pins. Following a PWM
PWMTM
2
SENSE
PWMDT
returns
REV. A
SENSE