MAX5886EGK+D Maxim Integrated Products, MAX5886EGK+D Datasheet - Page 9

• Manufacturer Part Number: MAX5886EGK+D
• Description: IC DAC 12BIT 3.3V 500MSPS 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX5886EGK+D

• Settling Time: 11ns
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 130mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-QFN Exposed Pad
• Number Of Dac Outputs: 1
• Conversion Rate: 500 MSPs
• Resolution: 12 bit
• Interface Type: Serial
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 3333 mW
• Minimum Operating Temperature: - 40 C
• Supply Current: 6.4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ended output voltages. The differential voltage existing
between IOUTP and IOUTN can also be converted to a
single-ended voltage using a transformer or a differen-
tial amplifier configuration. If no transformer is used, the
output should have a 50Ω termination to the analog
ground and a 50Ω resistor between the outputs.
Figure 1. Simplified MAX5886 Block Diagram
Table 1. I
*Terminated into a 50Ω load.
Performance DAC with Differential LVDS Inputs
FULL-SCALE CURRENT
I
OUT
FSADJ
REFIO
CLKP
CLKN
10
15
20
OUT
2
5
(mA)
and R
_______________________________________________________________________________________
REFERENCE
1.2V
DV
SET
DD
REFERENCE CURRENT
3.3V, 12-Bit, 500Msps High Dynamic
Selection Matrix Based on a Typical 1.200V Reference Voltage
DGND
I
REF
156.25
468.75
312.5
62.5
625
(µA)
DIFFERENTIAL DIGITAL INPUTS B0 THROUGH B11
LVDS RECEIVER/INPUT LATCH
SEGMENT SHUFFLING/LATCH
CURRENT-STEERING
MAX5886
CALCULATED
DECODER
DAC
12
19.2
7.68
3.84
2.56
1.92
Although not recommended because of additional
noise pickup from the ground plane, for single-ended
operation IOUTP should be selected as the output, with
IOUTN connected to AGND. Note that a single-ended
output configuration has a higher 2nd-order harmonic
distortion at high output frequencies than a differential
output configuration.
R
SET
(kΩ)
1% EIA STD
SEL0
19.1
3.83
2.55
1.91
7.5
SELECTION
FUNCTION
BLOCK
PD
OUTPUT VOLTAGE
V
IOUTP/N
IOUTN
IOUTP
AGND
AV
1000
DD
100
250
500
750
* (mV
P-P
)
9