MAX5886EGK+D Maxim Integrated Products, MAX5886EGK+D Datasheet - Page 10

• Manufacturer Part Number: MAX5886EGK+D
• Description: IC DAC 12BIT 3.3V 500MSPS 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX5886EGK+D

• Settling Time: 11ns
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 130mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-QFN Exposed Pad
• Number Of Dac Outputs: 1
• Conversion Rate: 500 MSPs
• Resolution: 12 bit
• Interface Type: Serial
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 3333 mW
• Minimum Operating Temperature: - 40 C
• Supply Current: 6.4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 3 displays a simplified diagram of the
MAX5886’s internal output structure.
The MAX5886 features a flexible differential clock input
(CLKP, CLKN) operating from separate supplies
(VCLK, CLKGND) to achieve the lowest possible jitter
performance. The two clock inputs can be driven from
a single-ended or a differential clock source. For sin-
gle-ended operation, CLKP should be driven by a logic
source, while CLKN should be bypassed to AGND with
a 0.1µF capacitor.
The CLKP and CLKN pins are internally biased to 1.5V.
This allows the user to AC-couple clock sources directly
to the device without external resistors to define the DC
level. The input resistance of CLKP and CLKN is >5kΩ.
See Figure 4 for a convenient and quick way to apply a
differential signal created from a single-ended source
(e.g., HP 8662A signal generator) and a wideband
transformer. These inputs can also be driven from an
LVDS-compatible clock source; however, it is recom-
mended to use sinewave or AC-coupled ECL drive for
best performance.
Figure 5 shows the timing relationship between differ-
ential, digital LVDS data, clock, and output signals. The
MAX5886 features a 1.8ns hold, a -0.8ns setup, and a
1.8ns propagation delay time. There is a 3.5 clock-
3.3V, 12-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
Figure 2. Reference Architecture, Internal Reference
Configuration
10
I
REF
I
REF
______________________________________________________________________________________
= V
REFIO
0.1µF
R
DACREF
/R
SET
FSADJ
REFIO
SET
REFERENCE
10kΩ
1.2V
Clock Inputs (CLKP, CLKN)
Data Timing Relationship
CURRENT-STEERING
DAC
AV
DD
IOUTP
IOUTN
cycle latency between CLKP/CLKN transitioning
high/low and IOUTP/IOUTN.
The MAX5886 features LVDS receivers on the bus input
interface. These LVDS inputs (B0P/N through B11P/N)
allow for a low-differential voltage swing with low con-
stant power consumption across a large range of
frequencies. Their differential characteristic supports
the transmission of high-speed data patterns without
the negative effects of electromagnetic interference
(EMI). All MAX5886 LVDS inputs feature on-chip termi-
nation with differential 100Ω resistors. See Figure 6 for
a simplified block diagram of the LVDS inputs.
Figure 3. Simplified Analog Output Structure
Figure 4. Differential Clock Signal Generation
SWITCHES
CURRENT
CLOCK SOURCE
(e.g., HP 8662A)
SINGLE-ENDED
AV
DD
WIDEBAND RF TRANSFORMER
PERFORMS SINGLE-ENDED TO
DIFFERENTIAL CONVERSION.
LVDS-Compatible Digital Inputs
CURRENT
SOURCES
1:1
CLKGND
(B0P–B11P, B0N–B11N)
25Ω
25Ω
0.1µF
0.1µF
I
OUT
IOUTN
CLKP
CLKN
DAC
TO
IOUTP
I
OUT