MAX5886EGK+D Maxim Integrated Products, MAX5886EGK+D Datasheet - Page 11

• Manufacturer Part Number: MAX5886EGK+D
• Description: IC DAC 12BIT 3.3V 500MSPS 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX5886EGK+D

• Settling Time: 11ns
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 130mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-QFN Exposed Pad
• Number Of Dac Outputs: 1
• Conversion Rate: 500 MSPs
• Resolution: 12 bit
• Interface Type: Serial
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 3333 mW
• Minimum Operating Temperature: - 40 C
• Supply Current: 6.4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A common-mode level of 1.25V and an 800mV differen-
tial input swing can be applied to these inputs.
Segment shuffling can improve the SFDR of the
MAX5886. The improvement is most pronounced at
higher output frequencies and amplitudes. Note that an
improvement in SFDR can only be achieved at the cost
of a slight increase in the DAC’s noise floor.
Pin SEL0 controls the segment-shuffling function. If
SEL0 is pulled low, the segment-shuffling function of
the DAC is disabled. SEL0 can also be left open,
because an internal pulldown resistor helps to deacti-
vate the segment-shuffling feature. To activate the
MAX5886 segment-shuffling function, SEL0 must be
pulled high.
The MAX5886 also features an active-high power-down
mode, which allows the user to cut the DAC’s current
consumption. A single pin (PD) is used to control the
power-down mode (PD = 1) or reactivate the DAC (PD
= 0) after power-down. Enabling the power-down mode
of the MAX5886 allows the overall power consumption
to be reduced to less than 1mW. The MAX5886
requires 10ms to wake up from power-down and enter
a fully operational state.
Figure 5. Detailed Timing Relationship
Performance DAC with Differential LVDS Inputs
B0 TO B15
CLKN
CLKP
IOUT
N - 5
______________________________________________________________________________________
DIGITAL DATA IS LATCHED ON
THE RISING EDGE OF CLKP
t SETUP
Power-Down Operation (PD)
Segment Shuffling (SEL0)
N - 1
3.3V, 12-Bit, 500Msps High Dynamic
t HOLD
N - 4
OUTPUT DATA IS UPDATED ON
THE FALLING EDGE OF CLKP
t PD
N
N - 3
The differential voltage existing between IOUTP and
IOUTN can also be converted to a single-ended volt-
age using a transformer (Figure 7) or a differential
amplifier configuration. Using a differential transformer-
coupled output, in which the output power is limited to
0dBm, can optimize the dynamic performance.
However, make sure to pay close attention to the trans-
former core saturation characteristics when selecting a
transformer for the MAX5886. Transformer core satura-
tion can introduce strong 2nd-harmonic distortion,
especially at low output frequencies and high signal
amplitudes. It is also recommended to center tap the
transformer to ground. If no transformer is used, each
DAC output should be terminated to ground with a 50Ω
resistor. Additionally, a 100Ω resistor should be placed
between the outputs (Figure 8).
Figure 6. Simplified LVDS-Compatible Input Structure
B0P–B11P
B0N–B11N
100Ω
Applications Information
N + 1
Differential Coupling Using a
N - 2
Wideband RF Transformer
t CH
CLOCK
t CL
D
D
N + 2
N - 1
Q
Q
TO DECODE
LOGIC
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