AD9763ASTZ Analog Devices Inc, AD9763ASTZ Datasheet

IC DAC 10BIT DUAL 125MSPS 48LQFP

AD9763ASTZ

Manufacturer Part Number
AD9763ASTZ
Description
IC DAC 10BIT DUAL 125MSPS 48LQFP
Manufacturer
Analog Devices Inc
Series
TxDAC+®r
Datasheets

Specifications of AD9763ASTZ

Data Interface
Parallel
Settling Time
35ns
Number Of Bits
10
Number Of Converters
2
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
450mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Resolution (bits)
10bit
Sampling Rate
125MSPS
Input Channel Type
Parallel
Supply Voltage Range - Analog
3V To 5.5V
Supply Voltage Range - Digital
2.7V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9763-EBZ - BOARD EVAL FOR AD9763
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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FEATURES
10-bit dual transmit DAC
125 MSPS update rate
Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc
Excellent gain and offset matching: 0.1%
Fully independent or single resistor gain control
Dual port or interleaved data
On-chip 1.2 V reference
Single 5 V or 3.3 V supply operation
Power dissipation: 380 mW @ 5 V
Power-down mode: 50 mW @ 5 V
48-lead LQFP
APPLICATIONS
Communications
Base stations
Digital synthesis
Quadrature modulation
GENERAL DESCRIPTION
The AD9763 is a dual port, high speed, 2-channel, 10-bit
CMOS DAC. It integrates two high quality 10-bit TxDAC+ cores,
a voltage reference, and digital interface circuitry into a small
48-lead LQFP. The AD9763 offers exceptional ac and dc
performance and supports update rates up to 125 MSPS.
The AD9763 is optimized for processing I and Q data in commu-
nications applications. The digital interface consists of two
double-buffered latches as well as control logic. Separate write
inputs allow data to be written to the two DAC ports, independent
of one another. Separate clocks control the update rate of the DACs.
A mode control pin allows the AD9763 to interface to two
separate data ports, or to a single interleaved high speed data
port. In interleaving mode, the input data stream is demuxed
into its original I and Q data and then latched. The I and Q data
are then converted by the two DACs and updated at half the
input data rate.
The GAINCTRL pin allows two modes for setting the full-scale
current (I
independently using two external resistors, or I
DACs can be set by using a single external resistor (see the Gain
Control Mode section for important date code information on
this feature).
The DACs utilize a segmented current source architecture
combined with a proprietary switching technique to reduce
glitch energy and to maximize dynamic accuracy. Each DAC
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
OUTFS
) of the two DACs. I
OUTFS
for each DAC can be set
OUTFS
for both
10-Bit, 125 MSPS Dual TxDAC+
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
provides differential current output, thus supporting single-ended
or differential applications. Both DACs can be simultaneously
updated and provide a nominal full-scale current of 20 mA. The
full-scale currents between each DAC are matched to within 0.1%.
The AD9763 is manufactured on an advanced, low cost, CMOS
process. It operates from a single supply of 3.3 V to 5.0 V and
consumes 380 mW of power.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
PORT1
PORT2
WRT1
WRT2
Digital-to-Analog Converter
The AD9763 is a member of a pin-compatible family of
dual TxDACs providing 8-bit, 10-bit, 12-bit, and 14-bit
resolution.
Dual 10-Bit, 125 MSPS DACs: A pair of high performance
DACs optimized for low distortion performance provide
for flexible transmission of I and Q information.
Matching: Gain matching is typically 0.1% of full scale, and
offset error is better than 0.02%.
Low Power: Complete CMOS dual DAC function operates
on 380 mW from a 3.3 V to 5.0 V single supply. The DAC
full-scale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.
On-Chip Voltage Reference: The AD9763 includes a 1.20 V
temperature-compensated band gap voltage reference.
Dual 10-Bit Inputs: The AD9763 features a flexible dual-
port interface allowing dual or interleaved input data.
DVDD
FUNCTIONAL BLOCK DIAGRAM
INTERFACE
DIGITAL
MODE
DCOM
©2006 Analog Devices, Inc. All rights reserved.
AVDD
AD9763
LATCH
LATCH
Figure 1.
1
2
ACOM
GENERATOR
REFERENCE
CLK1
CLK2
DAC
DAC
BIAS
2
1
AD9763
www.analog.com
I
I
REFIO
FSADJ1
FSADJ2
GAINCTRL
SLEEP
I
I
OUTA1
OUTB1
OUTA2
OUTB2
®

Related parts for AD9763ASTZ

AD9763ASTZ Summary of contents

Page 1

FEATURES 10-bit dual transmit DAC 125 MSPS update rate Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc Excellent gain and offset matching: 0.1% Fully independent or single resistor gain control Dual port or interleaved data On-chip 1.2 V ...

Page 2

AD9763 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 Dynamic Specifications ............................................................... 4 Digital Specifications ................................................................... 5 ...

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SPECIFICATIONS DC SPECIFICATIONS AVDD = 3 DVDD = 3 MIN MAX Table 1. Parameter RESOLUTION DC ACCURACY Integral Linearity Error (INL) Differential Linearity Error (DNL) ANALOG OUTPUT ...

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AD9763 DYNAMIC SPECIFICATIONS AVDD = 3 DVDD = 3 MIN MAX terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (f ) CLK ...

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DIGITAL SPECIFICATIONS AVDD = 3 DVDD = 3 MIN MAX Table 3. Parameter DIGITAL INPUTS Logic 1 Voltage @ DVDD = 5 V Logic 1 Voltage @ ...

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AD9763 ABSOLUTE MAXIMUM RATINGS Table 4. With Parameter Respect to AVDD ACOM DVDD DCOM ACOM DCOM AVDD DVDD MODE, CLK1, CLK2, DCOM WRT1, WRT2 Digital Inputs DCOM ACOM OUTA1 OUTA2 OUTB1 OUTB2 REFIO, FSADJ1, ACOM ...

Page 7

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DB9P1 (MSB) DB0P1 (LSB CONNECT Table 6. Pin Function Descriptions Pin No. Name PORT1 15, 21 DCOM1, DCOM2 16, 22 DVDD1, DVDD2 ...

Page 8

AD9763 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 5 V, DVDD = 3 mA, 50 Ω doubly terminated load, differential output, T OUTFS otherwise noted 5MSPS 25MSPS 70 65MSPS (MHz) OUT ...

Page 9

A (dBFS) OUT Figure 10. Single-Tone SFDR vs OUT OUT 85 5MHz/25MSPS 80 1MHz/5MSPS 75 2MHz/10MSPS 70 65 13MHz/65MSPS 60 ...

Page 10

AD9763 1MHz 80 OUT 10MHz OUT 25MHz OUT 40MHz OUT 60MHz OUT 45 –60 –40 – TEMPERATURE (°C) Figure 16. ...

Page 11

TERMINOLOGY Linearity Error or Integral Nonlinearity (INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (DNL) DNL is ...

Page 12

AD9763 THEORY OF OPERATION FSADJ1 R 1 SET REFIO 2kΩ 0.1µF FSADJ2 R 2 SET 2kΩ AD9763 1.2V REF WRT1/ GAINCTRL IQWRT DVDD 50Ω DCOM RETIMED CLOCK OUTPUT* LECROY 9210 PULSE GENERATOR Figure 21. Basic AC Characterization Test Setup for ...

Page 13

The full-scale output current of each DAC is regulated by separate reference control amplifiers and can be set from via an external resistor (R ) connected to the full SET scale adjust (FSADJ) pin. The ...

Page 14

AD9763 function of the reference current I OUTFS nominally set by a reference voltage (V REFIO resistor can be expressed as SET × I OUTFS REF where ...

Page 15

DIGITAL INPUTS The digital inputs of the AD9763 consist of two independent channels. For the dual port mode, each DAC has its own dedicated 10-bit data port, WRT line, and CLK line. In the interleaved timing mode, the function of ...

Page 16

AD9763 Timing specifications for interleaved mode are shown in Figure 28 and Figure 29. The digital inputs are CMOS compatible with logic thresholds set to approximately half the digital positive supply THRESHOLD (DVDD DVDD/2 (±20%) ...

Page 17

INPUT CLOCK AND DATA TIMING RELATIONSHIP SNR in a DAC is dependent on the relationship between the position of the clock edges and the point in time when the input data changes. The AD9763 is rising edge triggered, and so ...

Page 18

AD9763 DAC OUTPUT CONFIGURATIONS The following sections illustrate some typical output configura- tions for the AD9763. Unless otherwise noted assumed that I is set to a nominal 20 mA. For applications requiring the OUTFS optimum dynamic performance, a ...

Page 19

The differential circuit shown in Figure 37 provides the necessary level shifting required in a single-supply system. In this case, AVDD, the positive analog supply for both the AD9763 and the op amp, is also used to level shift the ...

Page 20

AD9763 Note that the units in Figure 40 are given in units of amps out/ volts in. Noise on the analog power supply has the effect of modulating the internal current sources and, therefore, the output current. The voltage noise ...

Page 21

APPLICATIONS USING THE AD9763 FOR QUADRATURE AMPLITUDE MODULATION (QAM) QAM is one of the most widely used digital modulation schemes in digital communications systems. This modulation technique can be found in FDM as well as spread spectrum (CDMA) based systems. ...

Page 22

AD9763 I and Q digital data can be fed into the AD9763 in two different ways. In dual port mode, the Digital I information drives one input port, while the Digital Q information drives the other input port ...

Page 23

EVALUATION BOARD GENERAL DESCRIPTION The AD9763- evaluation board for the AD9763 10-bit dual digital-to-analog converter. Careful attention to layout and circuit design, combined with a prototyping area, allow the user to easily and effectively evaluate the AD9763 in ...

Page 24

AD9763 RP5, 10Ω INP1 RP5, 10Ω INP2 RP5, 10Ω INP3 RP5, 10Ω INP4 RP5, 10Ω INP5 10 P1 ...

Page 25

DVDD VAL 0.01µF 0.1µ DVDD DB9P1 (MSB) DUTP1 1 MODE 48 DUTP2 DB8P1 AVDD 2 47 DUTP3 3 DB7P1 I 46 OUTA1 DUTP4 DB6P1 OUTB1 DUTP5 5 DB5P1 ...

Page 26

AD9763 Figure 48. Assembly, Top Side Figure 49. Assembly, Bottom Side Rev Page ...

Page 27

Figure 50. Layer 1, Top Side Figure 51. Layer 2, Ground Plane Rev Page AD9763 ...

Page 28

AD9763 Figure 52. Layer 3, Power Plane Figure 53. Layer 4, Bottom Side Rev Page ...

Page 29

... PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range AD9763AST –40°C to +85°C AD9763ASTRL –40°C to +85°C AD9763ASTZ 1 –40°C to +85°C 1 AD9763ASTZRL –40°C to +85°C AD9763- Pb-free part. 9.20 9.00 SQ 0.75 1.60 8.80 0.60 MAX 0.45 48 ...

Page 30

AD9763 NOTES Rev Page ...

Page 31

NOTES Rev Page AD9763 ...

Page 32

AD9763 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00617-0-9/06(D) Rev Page ...

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