CS4341-CZZ Cirrus Logic Inc, CS4341-CZZ Datasheet - Page 26

• Manufacturer Part Number: CS4341-CZZ
• Description: IC DAC STER 24BIT 96KHZ 16TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4341-CZZ

• Data Interface: Serial
• Number Of Bits: 24
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 90mW
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 24bit
• Sampling Rate: 96kSPS
• Input Channel Type: Serial
• Supply Current: 15mA
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1050-5

26
DIF2
6.2.4 POPGUARD
6.2.2 DIGITAL INTERFACE FORMAT (DIF)
6.2.3 DE-EMPHASIS CONTROL (DEM)
6.2.5 POWER DOWN (PDN)
0
0
0
0
1
1
1
1
Function:
Function:
Function:
Function:
Default = 000 - Format 0 (I²S, up to 24-bit data,
The required relationship between the Left/Right clock, serial clock and serial data is defined by the
Digital Interface Format and the options are detailed in Figures
Default = 00
00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz
Implementation of the standard 15µs/50µs digital de-emphasis filter response, Figure 20, requires re-
configuration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample
rates.
NOTE: De-emphasis is only available in Single-Speed Mode.
Default = 1
0 - Disabled
1 - Enabled
The Popguard
the quiescent voltage during power-on or power-down. Please refer to section 4.6 for implementation
details.
Default = 1
0 - Disabled
1 - Enabled
The device will enter a low-power state when this function is enabled. The power-down bit defaults to
‘enabled’ on power-up and must be disabled before normal operation can occur. The contents of the
control registers are retained in this mode.
DIF1
0
0
1
1
0
0
1
1
®
TRANSIENT CONTROL (POR)
DIF0
®
0
1
0
1
0
1
0
1
Transient Control allows the quiescent voltage to slowly ramp to and from 0 volts to
BIT 0
I²S, up to 24-bit data, 64Fs Internal SCLK
I²S, up to 16-bit data, 32Fs Internal SCLK
Left Justified, up to 24-bit data,
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 16-bit data
Right Justified, 18-bit data
Identical to Format 1
Table 5. Digital Interface Format
BIT 2-3
BIT 4-6
DESCRIPTION
BIT 1
64 x Fs Internal SCLK
17
through
)
Format
19
.
0
1
2
3
4
5
6
1
CS4341
FIGURE
DS298F5
17
17
18
19
19
19
19
17