CS4341-CZZ Cirrus Logic Inc, CS4341-CZZ Datasheet - Page 19

• Manufacturer Part Number: CS4341-CZZ
• Description: IC DAC STER 24BIT 96KHZ 16TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4341-CZZ

• Data Interface: Serial
• Number Of Bits: 24
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 90mW
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 24bit
• Sampling Rate: 96kSPS
• Input Channel Type: Serial
• Supply Current: 15mA
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1050-5

4.4
The device includes on-chip digital de-emphasis. The Mode Control (address 01h) bits select either the
32, 44.1 or 48 kHz de-emphasis filter. Figure 20 shows the de-emphasis curve for F
The frequency response of the de-emphasis curve will scale proportionally with changes in sample
rate, Fs. Please see section 6.2.3 for the desired de-emphasis control.
De-emphasis is only available in Single-Speed Mode.
4.5
1) Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the
2) Bring RST high. The device will remain in a low power state with VQ low.
3) Load the desired register settings while keeping the PDN bit set to 1.
4) Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µS when
4.6
The CS4341 uses Popguard
power-down. This technology, when used with external DC-blocking capacitors in series with the audio
outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. It
is activated inside the DAC when RST is enabled/disabled and requires no other external control, aside
from choosing the appropriate DC-blocking capacitors.
4.6.1
DS298F5
appropriate frequencies, as discussed in section 4.2. In this state, the control port is reset to its default
settings and VQ will remain low.
the POR bit is set to 0. If the POR bit is set to 1, see section 4.6 for a complete description of power-
up timing.
When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to
AGND. Following a delay of approximately 1000 sample periods, each output begins to ramp to-
ward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach V
audio output begins. This gradual voltage ramping allows time for the external DC-blocking capac-
itors to charge to the quiescent voltage, minimizing the power-up transient.
De-Emphasis
Popguard
Power-Up Sequence
Power-Up
®
Transient Control
®
technology to minimize the effects of output transients during power-up and
-10dB
Gain
0dB
dB
Figure 20. De-Emphasis Curve
3.183 kHz
T1=50 µs
F1
10.61 kHz
F2
T2 = 15 µs
Frequency
s
equal to 44.1 kHz.
CS4341
Q
and
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