CS4341-CZZ Cirrus Logic Inc, CS4341-CZZ Datasheet - Page 21

• Manufacturer Part Number: CS4341-CZZ
• Description: IC DAC STER 24BIT 96KHZ 16TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4341-CZZ

• Data Interface: Serial
• Number Of Bits: 24
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 90mW
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 24bit
• Sampling Rate: 96kSPS
• Input Channel Type: Serial
• Supply Current: 15mA
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1050-5

4.9.1
4.9.2
4.9.2a
4.9.2b
4.9.3
DS298F5
INCR
7
0
When excess capacitive loading is present on the I²C clock line, pin 6 (SCL/CCLK) may not have
sufficient hysteresis to meet the standard I²C rise time specification. This prevents the use of com-
mon I²C configurations with a resistor pull-up. A workaround is achieved by placing a Schmitt Trig-
ger buffer, a 74HC14 for example, on the SCL line just prior to the CS4341. This will not affect the
operation of the I²C bus as pin 6 is an input only.
The MAP byte precedes the control port register byte during a write operation and is not available
again until after a start condition is initiated. During a read operation the byte transmitted after the
ACK will contain the data of the register pointed to by the MAP (see section 4.9.3 for write/read
details).
The device has a MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP.
If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR
is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes of suc-
cessive registers.
In the I²C Mode, data is clocked into and out of the bi-directional serial control data line, SDA, by
the serial control port clock, SCL. There is no CS pin. Pin AD0 enables the user to alter the chip
address (001000[AD0][R/W]) and should be tied to VA or AGND as required, before powering up
the device. If the device ever detects a high to low transition on the AD0/CS pin after power-up,
SPI mode will be selected.
Rise Time for Control Port Clock
Memory Address Pointer (MAP)
I²C Mode
INCR (Auto Map Increment)
MAP0-3 (Memory Address Pointer)
Reserved
6
0
Default = ‘0’
0 - Disabled
1 - Enabled
Default = ‘0000’
S C L
Reserved
5
0
Figure 21. I²C Buffer Example
V A
Reserved
4
0
MAP3
3
0
MAP2
2
0
P in 6
MAP1
1
0
CS4341
MAP0
0
0
21