CS4341-CZZ Cirrus Logic Inc, CS4341-CZZ Datasheet - Page 17

• Manufacturer Part Number: CS4341-CZZ
• Description: IC DAC STER 24BIT 96KHZ 16TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4341-CZZ

• Data Interface: Serial
• Number Of Bits: 24
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 90mW
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 24bit
• Sampling Rate: 96kSPS
• Input Channel Type: Serial
• Supply Current: 15mA
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1050-5

4.
4.1
The device operates in one of two operational modes determined by the Master Clock to Left/Right Clock
ratio (see section 4.2). Sample rates outside the specified range for each mode are not supported.
4.2
The device requires external generation of the master (MCLK) and left/right (LRCK) clocks. The device
also requires external generation of the serial clock (SCLK) if the internal serial clock is not used. The
LRCK, defined also as the input sample rate Fs, must be synchronously derived from MCLK according to
specified ratios. The specified ratios of MCLK to LRCK, along with several standard audio sample rates
and the required MCLK frequency, are illustrated in Tables 2 and 3.
*Requires MCLKDIV bit = 1 in the MCLK Control (address 00h) register.
4.2.1
DS298F5
Sample Rate
APPLICATIONS
Sample Rate
The device will enter the Internal Serial Clock Mode if no low to high transitions are detected on
the SCLK pin for 2 consecutive periods of LRCK. In this mode, the SCLK is internally derived and
synchronous with MCLK and LRCK. The SCLK/LRCK ratio is either 32, 48, or 64 depending upon
the MCLK/LRCK ratio and the Digital Interface Format selection (see Table 4).
Operation in the Internal Serial Clock mode is identical to operation with an external SCLK syn-
chronized with LRCK; however, External SCLK mode is recommended for system clocking appli-
cations.
Sample Rate Range/Operational Mode
System Clocking
(kHz)
(kHz)
88.2
44.1
Internal Serial Clock Mode
64
96
32
48
4 kHz - 50 kHz
50 kHz - 100 kHz
Input Sample Rate (Fs)
11.2896
12.2880
8.1920
256x
11.2896
12.2880
8.1920
Table 3. Double-Speed Mode Standard Frequencies
Table 2. Single-Speed Mode Standard Frequencies
128x
Table 1. CS4341 Speed Modes
12.2880
16.9344
18.4320
384x
12.2880
16.9344
18.4320
192x
Single-Speed Mode
Double-Speed Mode
MCLK (MHz)
MCLK (MHz)
16.3840
22.5792
24.5760
512x
16.3840
22.5792
24.5760
256x*
MODE
24.5760
33.8688
36.8640
768x*
24.5760
33.8688
36.8640
384x*
45.1584
49.1520
1024x*
32.768
CS4341
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