PIC16LF1847T-I/MV Microchip Technology, PIC16LF1847T-I/MV Datasheet - Page 317
![14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan](/photos/16/12/161255/qfn28_sml.jpg)
PIC16LF1847T-I/MV
Manufacturer Part Number
PIC16LF1847T-I/MV
Description
14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan
Manufacturer
Microchip Technology
Series
PIC® XLP™ mTouch™ 16Fr
Datasheet
1.PIC16F1847-EP.pdf
(408 pages)
Specifications of PIC16LF1847T-I/MV
Processor Series
PIC16LF
Core
RISC
Data Bus Width
10 bit
Program Memory Type
Flash
Program Memory Size
8 KB
Data Ram Size
1024 B
Interface Type
SPI, I2C
Maximum Clock Frequency
32 KHZ
Number Of Programmable I/os
15
Number Of Timers
3
Operating Supply Voltage
3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
UQFN-28
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
PIC16F1847T
Supply Current (max)
34 uA
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
Details
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27.0
The Capacitive Sensing (CPS) module allows for an
interaction with an end user without a mechanical
interface. In a typical application, the CPS module is
attached to a pad on a Printed Circuit Board (PCB),
which is electrically isolated from the end user. When the
end user places their finger over the PCB pad, a
capacitive load is added, causing a frequency shift in the
CPS module. The CPS module requires software and at
least one timer resource to determine the change in
frequency. Key features of this module include:
• Analog MUX for monitoring multiple inputs
• Capacitive sensing oscillator
• Multiple Power modes
• High power range with variable voltage references
• Multiple timer resources
• Software control
• Operation during Sleep
FIGURE 27-1:
2011 Microchip Technology Inc.
Note 1:
CPS10
CPS11
CPS0
CPS1
CPS2
CPS3
CPS4
CPS5
CPS6
CPS7
CPS8
CPS9
CAPACITIVE SENSING
MODULE
If CPSON = 0, disabling capacitive sensing, no channel is selected.
CPSON
CAPACITIVE SENSING BLOCK DIAGRAM
CPSCH<3:0>
Ref-
(1)
0
1
Capacitive
Oscillator
CPSOSC
CPSRM
Sensing
DAC
Ref+
CPSRNG<1:0>
CPSON
0
1
FVR
Ref.
Int.
T0CKI
Preliminary
T0XCS
CPSOUT
CPSCLK
0
1
F
SYNCC1OUT
SYNCC2OUT
OSC
T1GSEL<1:0>
T1CS<1:0>
/4
T1OSC/
F
F
T1CKI
T1G
OSC
OSC
0
1
/4
PIC16(L)F1847
TMR0CS
Timer0 Module
TMR0
Timer1 Module
Control Logic
Timer1 Gate
EN
TMR1H:TMR1L
Overflow
DS41453B-page 319
TMR0IF
Set
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