PIC16LF1847T-I/MV Microchip Technology, PIC16LF1847T-I/MV Datasheet - Page 209
![14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan](/photos/16/12/161255/qfn28_sml.jpg)
PIC16LF1847T-I/MV
Manufacturer Part Number
PIC16LF1847T-I/MV
Description
14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan
Manufacturer
Microchip Technology
Series
PIC® XLP™ mTouch™ 16Fr
Datasheet
1.PIC16F1847-EP.pdf
(408 pages)
Specifications of PIC16LF1847T-I/MV
Processor Series
PIC16LF
Core
RISC
Data Bus Width
10 bit
Program Memory Type
Flash
Program Memory Size
8 KB
Data Ram Size
1024 B
Interface Type
SPI, I2C
Maximum Clock Frequency
32 KHZ
Number Of Programmable I/os
15
Number Of Timers
3
Operating Supply Voltage
3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
UQFN-28
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
PIC16F1847T
Supply Current (max)
34 uA
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
Details
- Current page: 209 of 408
- Download datasheet (4Mb)
24.2.5
The Compare mode is dependent upon the system
clock (F
down during Sleep mode, the Compare mode will not
function properly during Sleep.
TABLE 24-4:
2011 Microchip Technology Inc.
APFCON0
CCP1CON
CCPR1L
CCPR1H
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CCP2CON
CCPR2L
CCPR2H
CCP3CON
CCPR3L
CCPR3H
CCP4CON
CCPR4L
CCPR4H
INTCON
PIE1
PIE2
PIE3
PIR1
PIR2
PIR3
T1CON
T1GCON
TMR1L
TMR1H
TRISA
TRISB
Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by Compare mode.
Name
OSC
*
Page provides register information.
COMPARE DURING SLEEP
) for proper operation. Since F
Capture/Compare/PWM Register Low Byte (LSB)
Capture/Compare/PWM Register High Byte (MSB)
Capture/Compare/PWM Register Low Byte (LSB)
Capture/Compare/PWM Register High Byte (MSB)
Capture/Compare/PWM Register Low Byte (LSB)
Capture/Compare/PWM Register High Byte (MSB)
Capture/Compare/PWM Register Low Byte (LSB)
Capture/Compare/PWM Register High Byte (MSB)
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
RXDTSEL SDO1SEL
TMR1GIE
TMR1GIF
TMR1GE
C1INTP
C2INTP
TRISA7
TRISB7
OSFIE
OSFIF
C1ON
C2ON
Bit 7
GIE
TMR1CS<1:0>
—
—
—
—
SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE
P1M<1:0>
P2M<1:0>
T1GPOL
C1INTN
C2INTN
TRISA6
TRISB6
C1OUT
C2OUT
PEIE
ADIE
C2IE
ADIF
Bit 6
C2IF
—
—
—
—
SS1SEL
TMR0IE
CCP4IE
CCP4IF
T1GTM
TRISA5
TRISB5
C1OE
C2OE
RCIE
RCIF
C1IE
Bit 5
C1IF
T1CKPS<1:0>
C1PCH<1:0>
C2PCH<1:0>
DC1B<1:0>
DC2B<1:0>
DC3B<1:0>
DC4B<1:0>
OSC
T1GSPM
is shut
P2BSEL
CCP3IE
CCP3IF
TRISA4
TRISB4
C1POL
C2POL
INTE
EEIE
Bit 4
TXIE
TXIF
EEIF
Preliminary
T1GGO/DONE
T1OSCEN
CCP2SEL
TMR6IE
SSP1IE
TMR6IF
TRISA3
TRISB3
BCL1IE
SSP1IF
BCL1IF
IOCE
Bit 3
24.2.6
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
registers, APFCON0 and APFCON1. To determine
which pins can be moved and what their default loca-
tions are upon a Reset, see
Pin Function”
—
—
—
—
P1DSEL
T1SYNC
T1GVAL
TMR0IF
CCP1IE
CCP1IF
TRISA2
TRISB2
C1SP
C2SP
ALTERNATE PIN LOCATIONS
CCP4M<3:0)>
Bit 2
CCP1M<3:0>
CCP2M<3:0>
CCP3M<3:0>
—
—
—
—
—
—
for more information.
PIC16(L)F1847
P1CSEL
TMR2IE
TMR4IE
TMR2IF
TMR4IF
TRISA1
TRISB1
C1HYS
C2HYS
INTF
Bit 1
—
—
—
C1NCH<1:0>
C2NCH<1:0>
T1GSS<1:0>
Section 12.1 “Alternate
CCP1SEL
TMR1ON
C1SYNC
C2SYNC
TMR1IE
CCP2IE
TMR1IF
CCP2IF
TRISA0
TRISB0
IOCF
Bit 0
DS41453B-page 209
—
—
Register
on Page
206*
206*
179*
179*
120
228
172
173
172
173
228
228
228
228
228
228
228
228
228
187
188
122
127
89
90
91
92
94
95
96
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