PIC16LF1847T-I/MV Microchip Technology, PIC16LF1847T-I/MV Datasheet - Page 100
![14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan](/photos/16/12/161255/qfn28_sml.jpg)
PIC16LF1847T-I/MV
Manufacturer Part Number
PIC16LF1847T-I/MV
Description
14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan
Manufacturer
Microchip Technology
Series
PIC® XLP™ mTouch™ 16Fr
Datasheet
1.PIC16F1847-EP.pdf
(408 pages)
Specifications of PIC16LF1847T-I/MV
Processor Series
PIC16LF
Core
RISC
Data Bus Width
10 bit
Program Memory Type
Flash
Program Memory Size
8 KB
Data Ram Size
1024 B
Interface Type
SPI, I2C
Maximum Clock Frequency
32 KHZ
Number Of Programmable I/os
15
Number Of Timers
3
Operating Supply Voltage
3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
UQFN-28
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
PIC16F1847T
Supply Current (max)
34 uA
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
Details
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PIC16(L)F1847
9.1.1
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
FIGURE 9-1:
TABLE 9-1:
DS41453B-page 100
Name
INTCON
IOCBF
IOCBN
IOCBP
PIE1
PIE2
PIE4
PIR1
PIR2
PIR4
STATUS
WDTCON
Legend:
Instruction Flow
SLEEP instruction
- SLEEP instruction will execute as a NOP.
- WDT and WDT prescaler will not be cleared
- TO bit of the STATUS register will not be set
- PD bit of the STATUS register will not be
(INTCON reg.)
Note
Interrupt flag
GIE bit
Instruction
Fetched
Instruction
Executed
CLKOUT
cleared.
OSC1
1:
2:
3:
4:
PC
(1)
(2)
— = unimplemented, read as ‘0’. Shaded cells are not used in Power-down mode.
WAKE-UP USING INTERRUPTS
XT, HS or LP Oscillator mode assumed.
CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference.
T
GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
TMR1GIE
TMR1GIF
OST
IOCBN7
IOCBP7
IOCBF7
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Inst(PC) = Sleep
OSFIE
OSFIF
Bit 7
GIE
—
—
—
—
Inst(PC - 1)
= 1024 T
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
PC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
OSC
IOCBF6
IOCBN6
IOCBP6
PEIE
ADIE
ADIF
Bit 6
C2IE
C2IF
(drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes.
—
—
—
—
Inst(PC + 1)
Sleep
PC + 1
WDTPS4
TMR0IE
IOCBN5
IOCBP5
IOCBF5
RCIE
RCIF
Bit 5
C1IE
C1IF
—
—
—
Processor in
Sleep
WDTPS3
IOCBN4
IOCBF4
IOCBP4
PC + 2
INTE
TXIE
EEIE
EEIF
Bit 4
TXIF
TO
Preliminary
—
—
T
OST (3)
WDTPS2
IOCBF3
IOCBN3
IOCBP3
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSP1IE
BCL1IE
SSP1IF
BCL1IF
IOCE
Bit 3
Interrupt Latency
Inst(PC + 2)
Inst(PC + 1)
PD
—
—
• If the interrupt occurs during or after the execu-
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
PC + 2
tion of a SLEEP instruction
- SLEEP instruction will be completely exe-
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared.
cuted
WDTPS1
IOCBN2
IOCBP2
TMR0IF
IOCBF2
CCP1IE
CCP1IF
Bit 2
—
—
—
—
Z
(4)
Dummy Cycle
PC + 2
WDTPS0
IOCBN1
IOCBF1
IOCBP1
TMR2IE
TMR2IF
BCL2IE
BCL2IF
Bit 1
INTF
DC
—
—
2011 Microchip Technology Inc.
Dummy Cycle
Inst(0004h)
0004h
SWDTEN
IOCBF0
IOCBN0
IOCBP0
TMR1IE
CCP2IE
TMR1IF
SSP2IE
CCP2IF
SSP2IF
IOCF
Bit 0
C
Inst(0005h)
Inst(0004h)
Register on
0005h
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